Multi-drain enhancement JFET logic (SITL) with complementary MOS

Details Multi-drain enhancement JFET logic (SITL) with complementary MOS Multi-drain enhancement JFET logic (SITL) with complementary MOS

1982-07-13

1987-10-13

Larkins, William D.

357 22, 357 43, 357 92, H01L 2704, H03K 19091

Patent

active

047002131

ABSTRACT:
A semiconductor integrated logic circuit comprises a load transistor having a carrier injecting region and a carrier extracting region and an inverter transistor having a source region, drain regions, channel regions each connected between the source region and each of the drain regions, and gate regions defining the respective channel regions therebetween. The extracting region is merged into the gate regions. The channel regions have such dimensions and an impurity concentration that the channels are closed with depletion layers extending from the gate regions at zero gate voltage. The gate regions constitute a logic input and the drains constitute logic outputs. The zero gate voltage renders the channels non-conductive and the raised voltage renders the channels conductive, thus realizing an inverter circuit useful for wired logics.

REFERENCES:
patent: 3828230 (1974-08-01), Nishizawa
patent: 3924265 (1975-12-01), Rodgers
patent: 3969632 (1976-07-01), Bobenrieth
patent: 4255671 (1981-03-01), Nonaka et al.
patent: 4259681 (1981-03-01), Nishizawa

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