Multi-dimensional error diffusion technique

Details Multi-dimensional error diffusion technique Multi-dimensional error diffusion technique

1992-11-06

1993-12-14

Mancuso, Joseph

Image analysis

Histogram processing

For setting a threshold

358465, 358466, 382 54, G06K 936

Patent

active

052710700

ABSTRACT:
A circuit for increasing the speed of conversion of image pixels from one number of bits to another by processing a plurality of pixels in parallel. The conversion of each pixel typically results in a new value and an error term which is divided up among adjacent pixels. By using a plurality of separate conversion circuits, one for each line, and by processing the xth pixel on one line in parallel with the x-2 pixel on the next line, the plurality of pixels can be processed in parallel. All circuits are identical except that the first circuit must get the error term of the line above it from memory, and the last of the parallel circuits must store in memory the error term for the next plurality of lines.

REFERENCES:
patent: 5121446 (1992-06-01), Yamada et al.
patent: 5121447 (1992-06-01), Tanioka et al.
patent: 5150429 (1992-09-01), Miller et al.
patent: 5153925 (1992-10-01), Tanioka et al.
patent: 5157741 (1992-10-01), Katayama

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