Multi-digit arithmetic logic circuit for fast parallel execution

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364783, G06F 750

Patent

active

041398947

ABSTRACT:
A simple and fast arithmetic member for multi-digit numbers. For each digit a module is provided which receives the digits of corresponding significance and which first forms two output carry signals therefrom, i.e. one as if the relevant module always receives an input carry signal (E) and one as if this module never receives an input carry signal (D). Between successive modules each time functionally identical configurations of logic elements are connected which, under the control of the input carry signal to the module (Ci) of next-lower significance, the two output carry signals (Di, Ei) thereof, and an enable signal, forms the input carry signal for the stage of next-higher significance (C(i+1)) in accordance with the formula

REFERENCES:
patent: 3100835 (1963-08-01), Bedrij
patent: 3316393 (1967-04-01), Ruthazer
patent: 3553446 (1971-01-01), Kruy
patent: 3993891 (1976-11-01), Beck et al.

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