Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2000-04-25
2002-03-19
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S111000, C438S123000, C438S124000
Reexamination Certificate
active
06358775
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor encapsulation method, and more particularly to a multi-die semiconductor encapsulation method what enables multiple dies to be encapsulated into an integrated circuit. The invention relates also to a multi-die semiconductor made according to this method.
Because modern computer systems are sophisticated, the effective capacity of related integrated circuits must be relatively expanded to meet the requirements. However, according to current chip manufacturing processes, the greater the capacity is the larger the chip dimension and the higher the chip manufacturing cost will be. Multi-die encapsulation can increase the capacity without increasing many dimensions.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide a semiconductor encapsulation method which enables multiple dies to be encapsulated into an integrated circuit. It is another object of the present invention to provide an integrated circuit which has multiple dies encapsulated in it. A multi-die semiconductor encapsulation method according to the present invention comprises the steps of:
(1) preparing a lead-frame having a center open area and parallel rows of pins around the center open area;
(2) preparing a substrate having a plurality of die positioning zones at the center area of the back side wall thereof, a window respectively disposed at the center of each die positioning zone, conductor elements respectively disposed at the top side wall thereof around each window, and peripheral rows of terminals;
(3) preparing a plurality of dies each having a plurality of solder tips and then fastening the dies to the die positioning zones at the substrate;
(4) using conductor wires to connect the solder tips at the dies to the conductor elements at the substrate;
(5) mounting the substrate in the center open area at the lead-frame and then connecting the terminals at the substrate to the pins at the lead-frame respectively; and
(6) encapsulating the assembly of the substrate, the lead frame and the die into a multi-die semiconductor.
A finished multi-die semiconductor in accordance with the present invention comprises:
a lead-frame, the lead-frame having a center open area, and parallel rows of pins disposed at least two of four peripheral sides thereof around the center open area;
a substrate mounted in the center open area at the lead frame, the substrate comprising a plurality of die positioning zones at the center area of a back side wall thereof, a window respectively disposed at the center of each of the die positioning zones, conductor elements respectively disposed at a top side wall thereof around each window, and rows of terminals disposed at least two of four peripheral sides thereof and respectively connected to the pins at the lead-frame;
a plurality of dies respectively mounted in the die positioning zones at the back side wall of the substrate, the dies each having a plurality of solder tips respectively suspended in the windows in the substrate corresponding to the conductor elements at the substrate; and
conductor wires respectively connected between the solder tips at the dies and the conductor elements at the substrate.
REFERENCES:
patent: 5278101 (1994-01-01), Ikenoue
patent: 5434106 (1995-07-01), Lim et al.
patent: 5763294 (1998-06-01), Lin
patent: 5858815 (1999-01-01), Heo et al.
patent: 5933708 (1999-08-01), Sim et al.
patent: 6066888 (2000-05-01), Yanagisawa
patent: 6200833 (2001-03-01), Jiang et al.
Picardat Kevin M.
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