Multi-die package

Details Multi-die package Multi-die package

2002-06-12

2003-05-27

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S698000, C257S723000, C257S724000, C257S730000

Reexamination Certificate

active

06570246

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a multi-die package.
2. Description of the Prior Art
It is now a leading trend for fabricating devices or electronic products, such as notebooks, PDAs and digital cameras with small, thin, light, multi-functional high-density packages for semiconductor devices that contain a high level of integration. Raising the integration level of a package depends on the size of package carrier and the space between the die and the carrier.
For a single die package, a lead on chip (LOC) package is commonly used to reduce the space between the die and the carrier. In the LOC frame, the leads of the carrier can be extended to the bonding pads in the center of the die and the leads are connected with the active surface of the die to provide the die with a physical support. Therefore, the size of package can be reduced. Wherein, the carrier is made of a conventional LOC lead frame or a laminate substrate with an opening.
For a multi-die package, a multi-chip module (MCM) is often seen in a high-density package. The MCM can simultaneously package many dies in one carrier according to different design demands. The MCM not only reduces the size of package, decreases the production costs and the signal transition path, but also increases bulk efficiency. The MCM is usually set up on a printed circuit board (PCB). A plurality of dies are arranged on a same surface of the PCB. The dies and the PCB are connected with each other by using a wire bonding technique, a tape automatic bonding (TAB) technique or a flip chip technique.
A conventional multi-die package
20
is explained with reference to
FIG. 1
to FIG.
2
. Referring to
FIG. 1
, an active surface of at least one die
12
is turned upward. An insulation glue
14
is smeared over a back of the die
12
, and the die
12
is mounted in a predetermined region of a plate
10
. The die
12
is baked and solidified at a temperature of about 150° C. Then, a wire bonding technique is utilized to electrically connect a bonding pad
16
of the die
12
and a corresponding terminal (not shown) of the plate
10
with a copper wiring
15
. A molding material
18
is used to enclose the die
12
and the copper wiring
15
and then the molding material
18
is baked to solidify. After that, an etching process is performed to form a plurality of solder ball pads (not shown) under the plate
10
, and a plurality of solder balls
19
are welded to the plurality of solder ball pads. The solder balls
19
are electrically connected to the package
20
and a PCB (not shown). An internal circuit (not shown) is arranged inside the plate
10
and electrically connected to the terminals of the plate
10
and the solder balls
19
, so the die
12
can electrically connect to a PCB by using the copper wiring
15
, the internal circuit in the plate
10
and the solder balls
19
. The plurality of solder ball pads are arrayed as a ball grid array (BGA). In addition, the plate
10
is a laminate substrate, the insulation glue
14
is made of polymer, and the molding material
18
is made of ceramic, glass epoxy or BT resin.
In the conventional wire bonding method, a square measure of the package is too large to conform to a requirement of small size. Therefore, a chip scale package is developed, which has a smaller distance between the solder balls. The chip scale package size is similar to a die, and the thickness of the chip scale package does not have to take into consideration a wiring radian height. The chip scale package is a high-density package by using a bare chip and a flip chip technique. Referring to
FIG. 2
, in the conventional flip chip scale package
28
, an active surface of at least one die
12
is turned downward and mounted on a predetermined surface of the plate
10
by using a flip chip technique. A plurality of bump pads
22
are located on the plate
10
electrically connected to corresponding solder balls
24
. The bonding pads
16
on the active surface of the die
12
are electrically connected to the corresponding bump pads
22
. A filling material
26
, such as resin is filled spaces between the die
12
and plate
10
, on the outside of the solder balls
24
. Thus, an under fill region (not shown) is formed to reduce a stress of the solder balls
24
generated from different thermal expansion coefficients of the plate
10
and the die
12
.
In the prior art multi-die package, the dies are arranged on the same side of the PCB. When too many dies are arranged on the PCB, a package square measure is larger and does not conform to a present leading trend. Transmission via circuit lines between each die are limited by a complicated transition path in the PCB. Due to the distance of the signal transition path is longer, the resistance is increased. Therefore, bulk efficiency is reduced. Although the flip chip technique is utilized to reduce the package size, the distances between bonding pads of the dies will become narrower due to the smaller size of die. The height of the solder ball is reduced to limit the gap between the filling material and the die. It is difficult to form the under fill region. A known good die method is utilized in the package presently, but the yield is low while costs are high.
SUMMARY OF INVENTION
It is therefore an object of the present invention to provide a multi-die package to reduce signal transition path between each die and raise bulk efficiency.
It is another objective of the present invention to provide a multi-die package. The package is not only mechanically strengthened to prevent the die from surrounding damage, collision, chemical material or moisture, but also reduces a bulk package size and raises package integration.
In accordance with the objective of the present invention includes: (
1
) an L-shaped plate comprising a die package region, a plurality of bump pads located in the die package region, a plurality of pins electrically connected to a printed circuit board (PCB), and an internal circuit arranged inside the L-shaped plate electrically connected to the plurality of bump pads and corresponding pins, and (
2
) a plurality of dies arranged in the die package region of the L-shaped plate, each die comprising a plurality of bonding pads on an active surface of the die, and the plurality of bonding pads are electrically connected to the corresponding solder bump pads.
The present invention utilizes the L-shaped plate as a package frame to package a plurality of dies with same or different functions for forming a package. If there are too many dies in the same package, the L-shaped plate can be extended to have a plurality of vertical plates and a plurality of die package regions. In addition, the package comprises a plurality of pins underside the L-shaped plate, therefore the package can be taken as a card structure. The package after an encapsulating process can be conveniently fabricated and changed by users. The dies and the interior circuit are prevented from damage.


REFERENCES:
patent: 5006925 (1991-04-01), Bregman et al.
patent: 5545924 (1996-08-01), Contolatis et al.
patent: 5817986 (1998-10-01), Davidson et al.
patent: 6078102 (2000-06-01), Crane et al.

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