Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-03-20
2004-05-04
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S686000, C257S723000, C257S738000, C257S780000, C257S778000
Reexamination Certificate
active
06731009
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuit assemblies, and more particularly to assemblies that include one or more integrated circuit dice.
BACKGROUND OF THE INVENTION
Integrated circuits are typically provided in some type of assembly package. The assembly can protect an integrated circuit from mechanical and/or environmental damage. As electronic devices continue to shrink in size, it can become increasingly desirable to provide packaged integrated circuits that occupy as small an area as possible on a circuit board or the like (have as small a “footprint” as possible).
In most assemblies, conductive paths to an integrated circuit are provided by way of a chip carrier (interposer) that includes a number of “leads.” The various leads of an integrated circuit can be then be connected to each other on a circuit board by traces. For some applications, the impedance presented by such traces can limit signal propagation speeds, require undesirably high drive current, and/or consume more power than desired. Along these same lines, many types of packages, due to bond wires and/or traces, may introduce unwanted inductance along a signal path. Such inductance can lead to “ground bounce” (unwanted fluctuations in a ground potential when current flows through a signal path) or other undesirable results.
It can also be desirable to provide as many circuit functions as possible in the same assembly. However, integrating multiple types of circuits within a single semiconductor substrate can be prohibitively expensive and/or add complexity to a manufacturing process.
One way to address the above concerns is to provide assemblies that include more than one integrated circuit device (“chip or die”). A number of conventional multi-chip assemblies will now be described.
FIGS. 8A and 8B
show a first conventional multi-chip assembly
800
.
FIG. 8A
shows a top plan view of a multi-chip assembly
800
. A multi-chip assembly may be a ball grid array (BGA) assembly that includes multiple dice
802
-
0
to
802
-
2
situated side-by-side on an assembly substrate
804
. Each die (
802
-
0
to
802
-
2
) may be connected to a substrate
804
by a conventional wire bond arrangement. An exemplary bond wire is indicated by the reference character
806
, and may connect a bond pad on a die (
802
-
0
to
802
-
2
) to a conductive trace (not shown in
FIG. 8A
) on a substrate
804
.
Various conductive traces on substrate
804
may connect various dice (
802
-
0
to
802
-
2
) to one another. Substrate traces may also provide a conductive path to solder balls (not shown in
FIG. 8A
) formed on a bottom of a substrate
804
.
FIG. 8B
shows a side cross-sectional view of an assembly
800
. One end of a bond wire
806
can be connected to a bond pad
808
on a die
802
-
0
. Another end of bond wire
806
can be connected to trace
810
on substrate
804
. A die
802
-
0
can be connected to a substrate
804
by a die attach
812
. As noted above, a trace
810
may provide a conductive path to solder balls
814
situated on an assembly bottom. Solder balls
814
may provide a BGA type connection for the multi-chip assembly
800
.
A multi-chip approach such as that set forth in
FIG. 8A and 8B
can provide multiple functions without having to form a larger integrated circuit. Such an approach may also provide some reduction in the footprint presented by the various chips (
802
-
0
to
802
-
2
) as traces formed on a substrate
804
may be shorter than traces of a circuit board. Shorter traces on a substrate
804
may require less current to drive and present smaller impedance than conventional circuit board traces.
A second conventional approach is shown in
FIGS. 9A and 9B
.
FIG. 9A
is a top plan view of a multi-chip assembly
900
according to another conventional example. A multi-chip assembly
900
, like the example of
FIGS. 8A and 8B
, can include dice
902
-
0
to
902
-
2
arranged in a side-by-side fashion. Unlike the example of
FIGS. 8A and 8B
, dice
902
-
0
to
902
-
2
may be connected to a substrate
904
by conductive bumps (e.g., in a “flip-chip” fashion). In a flip-chip arrangement, a die can include a bonding surface that faces an assembly substrate
904
. A number of connections can be provided between a bonding surface and traces in a substrate
904
by conductive structures such as bumps, or the like. Conductive connections between dice (
902
-
0
to
902
-
2
) and a substrate
904
are shown as dashed circles. One of the many connections is shown as item
906
. Like the arrangement of
FIGS. 8A and 8B
, various conductive traces (not shown) on a substrate
904
may connect various dice (
902
-
0
to
902
-
2
) to one another, and to solder balls (not shown in
FIG. 9A
) formed on a bottom of a multi-chip assembly
900
.
FIG. 9B
shows a side cross-sectional view of an assembly
900
. A number of conductive connections
906
may exist between a die
902
-
0
and an assembly substrate
904
. Solder balls
908
may provide a BGA type connection for a multi-chip assembly
900
.
As in the case of the example of
FIGS. 8A and 8B
, a multi-chip approach such as that set forth in
FIG. 9A and 9B
can provide multiple functions. A multi-chip assembly
900
may also have a smaller footprint than a multi-chip assembly
800
, as bond wire connections may require more area around the periphery of dice
802
-
0
to
802
-
2
than flip-chip type connections.
A drawback to the arrangements of
FIGS. 8A
,
8
B,
9
A and
9
B is that an assembly footprint may be no smaller than the combined area of the dice contained within the assembly.
A third conventional example is shown in FIG.
10
.
FIG. 10
shows a side cross-sectional view of multi-chip assembly
1000
. A multi-chip assembly
1000
may include dice
1002
-
0
and
1002
-
1
that are stacked one on top of the other. Die
1002
-
0
can be situated on an assembly substrate
1004
, while die
1002
-
1
can be situated on die
1002
-
0
. Lower bond wires, one of which is shown as item
1006
, can connect die
1002
-
0
to traces on a substrate
1004
. Higher bond wires, one of which is shown as
1008
, can connect die
1002
-
1
to traces on a substrate
1004
. Higher bond wires
1008
can extend over lower bond wires
1006
. Like the previously described examples, traces (not shown) on a substrate
1004
may connect dice
1002
-
0
to
1002
-
1
to one another and/or to solder balls
1010
formed on a bottom of a substrate
1004
.
A multi-chip packaging arrangement such as that shown in
FIG. 10
can provide multiple functions without having to form a larger integrated circuit. Such a multi-chip assembly
1000
can also provide a smaller footprint than the previously described examples, as the dice (
1002
-
0
and
1002
-
1
) may be stacked on top of one another, and not arranged in a side-by-side fashion. Traces on substrate
1004
can present smaller impedance than circuit board traces.
A drawback to the arrangement of
FIG. 10
arises out of a ratio between the sizes of the dice in the assembly. In particular, a top die may have to be smaller than a bottom die to allow bonding from a substrate to a bottom die. Further, a substrate may have to include sufficient area to allow upper bond wires to be formed over lower bond wires.
Yet another conventional example of a multi-chip assembly is shown in
FIG. 11
in a cross-sectional view. A multi-chip assembly
1100
may include multiple dice (
1102
-
0
to
1102
-
2
) having traces that extend from bond locations on a die surface to a die edge. Vertical traces may connect traces on dice edges to one another, and to solder balls
1104
on a bottom of an assembly
1100
. Connections may include gold traces insulated by a dielectric such as polyimide. In addition, or alternatively, connections may be made by “flex tape” which can include a flexible insulating tape having conductive traces formed within.
A multi-chip packaging arrangement such as that shown in
FIG. 11
can provide multiple functions, and a comparatively small footprint with respect to the other desc
Brophy Brenor
Jones Christopher W.
Cypress Semiconductor Corporation
Lee Eddie
Parekh Nitin
Sako Bradley T.
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