Multi-CPU unit

Details Multi-CPU unit Multi-CPU unit

2000-12-15

2002-10-08

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Distributed processing system

Reexamination Certificate

active

06463519

ABSTRACT:

TECHINAL FIELD
The present invention relates to a multi-CPU unit which is a programmable controller CPU unit used for industrial equipment and has a plurality of CPU units used for a multi-CPU control operation, and more particularly, to a multi-CPU unit in which the memory capacity can be reduced and the processing speed can be improved.
BACKGROUND ART
FIG. 11
is a structural diagram of a conventional multi-CPU unit, and
FIG. 12
is a diagram showing the detail of device memories and two-port memories for inter-CPU-unit communication in FIG.
11
. Referring to
FIG. 11
, a CPU unit
1
A comprises a microprocessor
2
A for transferring data in accordance with information which is obtained by decoding an OS program, an OS
26
A for transferring data between a device memory and a two-port memory for communication, a device memory
3
A for handling device data, e.g., D
0
and D
1
in a program which is processed by the CPU unit A, and a two-port memory
24
A for inter-CPU-unit communication which communicates data between the CPU units under multi-CPU control operation.
A CPU unit
1
B, which has the same configuration as that of the CPU unit
1
A, comprises a microprocessor
2
B for transferring data in accordance with information which is obtained by decoding an OS program, an OS
26
B for transferring data between a device memory and a two-port memory for communication, a device memory
3
B for handling device data, e.g., D
0
and D
1
in a program which is processed by the CPU unit B, and a two-port memory
24
B for inter-CPU-unit communication for communicating data between the CPU units under the multi-CPU control operation.
Further, a CPU unit
1
C, which has the same configuration as that of the CPU unit
1
A, comprises a microprocessor
2
C for transferring data in accordance with information which is obtained by decoding an OS program, an OS
26
C for transferring data between a device memory and a two-port memory for communication, a device memory
3
C for handling device data, e.g., D
0
and D
1
in a program which is processed by the CPU unit C, and a two-port memory
24
C for inter-CPU-unit communication for communicating data between the CPU units under the multi-CPU control operation.
Referring to
FIG. 12
, the device memory
3
A comprises a device data area
10
A for CPU unit
1
A, a device data area
11
A for CPU unit
1
B, and a device data area
12
A for CPU unit
1
C. The two-port memory
24
A for inter-CPU-unit communication comprises a data storing area
30
A for CPU unit
1
B and a data storing area
31
A for CPU unit
1
C.
The device memory
3
B comprises a device data area
10
B for CPU unit
1
A, a device data area
11
B for CPU unit
1
B, and a device data area
12
B for CPU unit
1
C. The two-port memory
24
A for inter-CPU-unit communication comprises a data storing area
30
B for CPU unit
1
A and a data storing area
31
B for CPU unit
1
C.
Further, the device memory
3
C comprises a device data area
10
C for CPU unit
1
A, a device data area
11
C for CPU unit
1
B, and a device data area
12
C for CPU unit
1
C. The two-port memory
24
C for inter-CPU-unit communication comprises a data storing area
30
C for CPU unit
1
A and a data storing area
31
C for CPU unit
1
B.
FIG.
13
and
FIG. 14
are flowcharts showing software which is built in the OSs
26
A,
26
B,,and
26
C in the CPUs and concerns data transfer between the device memories and the two ports for communication. Referring to
FIG. 13
, first, one is substituted for n so as to determine a CPU-unit number (step S
2202
), it is checked to see if n coincides with the CPU-unit number of one CPU-
7
unit (step S
2203
), the CPU unit is connected to the two-port memory for inter-CPU-unit communication of the CPU unit which is indicated by n if it is determined that n is different from the one CPU unit (step S
2204
), and further, the block position of the two-port memory for inter-CPU-unit communication to which device data is written is calculated on the basis of the number (steps S
2205
, S
2206
, and S
2207
). After writing the data to the two-port memory for inter-CPU-unit communication, the two-port memory for inter-CPU-unit communication in the CPU unit is separated (step S
2208
), the next number is obtained (step S
2209
), and it is checked to see if there are any more CPU units which are used for the multi-CPU control operation (step S
2210
). If NO, the processing routine is completed (step S
2211
) and, if YES, the series of the operations is repeated again (steps. S
2203
to S
2210
).
Here, a conventional technique-will be described in accordance with the sequence.
As shown in
FIG. 11
, the multi-CPU unit comprises the three units of the CPU units
1
A,
1
B, and
1
C. The CPU units
1
A,
1
B, and
1
C comprise the device memories
3
A,
3
B, and
3
C having the device data areas for CPU units
1
A,
1
B, and
1
C, and the two-port memories
24
A,
24
B, and
24
C for inter-CPU-unit communication for communication with the two CPU units other than the one CPU unit of the CPU units
1
A,
1
B, and
1
C, respectively, as shown in FIG.
11
.
The CPU units
1
A,
1
B, and
1
C have CPU-unit numbers thereof which are determined by numbers written to the OSs
26
A,
26
B, and
26
C which the CPU units
1
A,
1
B, and
1
C have, respectively. The CPU-unit number gives which number the one CPU unit has under the multi-CPU control operation. Herein, the CPU-unit number of the CPU unit
1
A is labeled as
1
, the CPU-unit number of the CPU unit
1
B as
2
, and the CPU-unit number of the CPU unit
1
C as
3
..
To start with, in order to communicate the contents of the device data area
10
A for CPU unit
1
A to the CPU unit
1
B, the OS
26
A connects the CPU unit
1
A to the two-port memory
24
B for inter-CPU-unit communication in the CPU unit
1
B via a communication line
7
B. From the CPU-unit number, it is calculated to where the contents of the device data area
10
A for CPU unit
1
A are to be written in the two-port memory
24
B for inter-CPU-unit communication in the CPU unit
1
B. According to the calculating method, the CPU-unit number of the one CPU unit is compared with the CPU-unit number of the CPU unit which has the contents to be written, the contents are written to the portion of the CPU-unit number of the one CPU-unit (the portion becomes the first, if the CPU-unit number is
1
) if the CPU-unit number of the one CPU unit is smaller, and the contents are written to the portion which is obtained by subtracting one from the CPU-unit number of the one CPU unit (the portion becomes the (
2
-
1
)th portion, that is, the first, if the CPU-unit number is
2
) if the CPU-unit number of the one CPU unit is larger. Since the CPU-unit number of the CPU unit
1
A is land the CPU-unit number of the CPU unit
1
B is
2
, the CPU-unit number of the CPU unit
1
A is smaller. Consequently, the OS
26
A in the CPU unit
1
A writes the data to the data storing area
30
B for CPU unit
1
A which exists at the first area in the two-port memory
24
B for inter-CPU-unit communication, via a communication line
5
A in the CPU unit
1
A and the communication line
71
in the CPU unit
1
B.
By using a method similar thereto, the OS
26
A in the CPU unit
1
A writes the data of the device data area
10
A for CPU unit
1
A in the device memory
3
A in the CPU unit
1
A to the data storing area
30
C for CPU unit
1
A in the two-port memory
24
C for inter-CPU-unit communication in the CPU unit
1
C, via the communication line
5
A in the CPU unit
1
A and a communication line
7
C in the CPU unit
1
C.
By using a sequence similar thereto, the OS
26
B in the CPU unit
1
B writes the data of the device data area
11
B for CPU unit
1
B in the device memory
3
B in the CPU unit
1
B to the data storing area
30
A for CPU unit
1
B in the two-port memory
24
A for inter-CPU-unit communication in the CPU unit
1
A, via a communication line
5
B in the CPU unit
1
B and a communication line
7
A in the CPU unit
1
A. The OS
26
B in the CPU unit
1
B also writes the data to the data storing ar

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