Multi-CPU system using common memory and having access mediation

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364239, 3642426, 36424293, 3642281, 364DIG1, 395325, G06F 1314

Patent

active

051558556

ABSTRACT:
A multi-CPU system comprises between a CPU without a control terminal and a common memory: an access mediation latch for temporarily latching data information to be transferred and corresponding address information; and a timing control circuit for controlling the timing of data transfer between the access mediation latch and the common memory in accordance with a mediation signal outputted from a contention mediation terminal of the common memory.

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