Multi-core stream processor having (N) processing units and...

Details Multi-core stream processor having (N) processing units and... Multi-core stream processor having (N) processing units and...

2009-05-05

2011-10-11

Faherty, Corey S (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S205000, C712S206000

Reexamination Certificate

active

08037283

ABSTRACT:
In a multi-core stream processing system and scheduling method of the same, a scheduler is coupled to a number (N) of stream processing units and a number (N+1) of stream fetching units, where N≧2. When the scheduler receives a stream element from a Pthstream fetching unit, the scheduler assigns a Pthstream processing unit as a target stream processing unit when the Pthstream processing unit does not encounter a bottleneck condition, assigns a Qthstream processing unit, which does not encounter the bottleneck condition, as the target stream processing unit when the Pthstream processing unit encounters the bottleneck condition, where 1≦P≦N, 1≦Q≦N, and P≠Q, and dispatches the received stream element to the target stream processing unit such that the target stream processing unit processes the stream element dispatched from the scheduler.

REFERENCES:
patent: 2005/0013705 (2005-01-01), Farkas et al.
patent: 2009/0174706 (2009-07-01), Howson
patent: 2009/0300327 (2009-12-01), Omtzigt
Khailany et al.; Imagine: Media Processing with Streams; 2001; IEEE.
Benjamin et al.; Stream Processing on a Dual-Core Embedded System; 2007; SAMOS 2007, LNCS 4599, pp. 149-158.
Zhou; Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window; 2005; IEEE.

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