Multi-connection via with electrically isolated segments

Details Multi-connection via with electrically isolated segments Multi-connection via with electrically isolated segments

1999-07-23

2002-05-14

Cuneo, Kamand (Department: 2841)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C333S246000, C174S260000, C361S794000, C257S774000

Reexamination Certificate

active

06388208

ABSTRACT:

GOVERNMENT RIGHTS
Not applicable.
FIELD OF THE INVENTION
This invention relates generally to electrical connections between layers of multi-layer printed circuit boards and more particularly to a class of layer-to-layer interconnections referred to as via circuits or more simply vias.
BACKGROUND OF THE INVENTION
As is known in the art, there exists a class of electrical connection structures, referred to as plated through holes (PTHs) or via circuits or more simply vias, which provide layer-to-layer interconnections in multi-layer printed circuit boards (PCBs).
A conventional via in a multi-layer PCB is typically provided by drilling or otherwise forming a hole through the PCB. The through hole passes through all conductive layer traces in the PCB which are intended to be connected. The hole is then plated to form an electrical connection among the conductive traces. In this manner, electrical connections between layers of multi-layer PCBs can be provided. This process can be used to provide a signal path through which a single signal propagates between layers of a PCB. Connections to conductive traces or signal paths in each of the PCB layers can be made. This via connection technique conserves space on the PCB and thus allows PCBs to be more densely populated.
The via has been the mainstay of layer-to-layer interconnection since the inception of double-sided and multi-layer boards. Originally vias served dual purposes, providing layer-to-layer interconnect and through-hole component mount. The growth of surface mount component technology (with the exception of backplane connectors and other large devices), however, has reduced the need to utilize vias for through-hole component mount and has resulted in the via primarily providing layer-to-layer interconnection.
There has, however, been a trend to provide PCBs having increasingly higher circuit density and higher circuit speed. To help meet the demand for increased circuit density, it has been proposed to provide more than one independent signal path or connection in a single via. To provide multiple connections in the same via of a PCB, the via is formed as described above. Discrete connections are then formed among the conductive traces of the PCB by establishing grooves in the plating of the via to electrically isolate segments of the PCB. This technique permits two or more independent connections to be made in the same via of a multi-layer PCB. This technique further conserves space on the PCB and thus allows PCBs to be even more densely populated.
Despite the advances made in increasing circuit density on PCBs, the high performance requirements of modern integrated circuit (IC) devices impose requirements for increasingly higher density of interconnections on PCBs so that the PCBs can accept the large number of input and output signal lines from IC devices which are packaged into increasingly smaller volumes. All of these design and performance considerations add to the difficulties in attempting to lower PCB production costs which are increasing due to the use of complicated multiple-layer substrates.
Furthermore, modem IC devices operates at increasingly higher frequencies. As clock frequencies of circuits used on PCBs exceed 100 MHz, the electrical characteristics of PCB traces resemble high-speed signal transmission lines rather than D.C. electrical circuits. The higher clock frequencies and resultant shorter signal rise times expose PCB performance limitations which are manifested by signal integrity phenomena such as ringing, reflections, ground bounce, and crosstalk.
State of the art computer motherboards operate at frequencies of 100 MHz and above, while telecommunications and high performance systems use device to board frequencies an order of magnitude higher. High performance systems having chip-to-board clock speeds in the GHz range are expected. To support these current and future performance demands, improvement gains in PCB technology are required.
To address the above density and speed concerns “buildup technologies” such as photo-via redistribution, and sheet buildup, have been developed. These techniques have increased PCB performance significantly. These techniques, however, rely on thinner layers and use chemical etching (photo-defined vias), laser ablation, or plasma etching technologies to drill holes and connect PC board layers. Thus, such techniques are not appropriate for use in PCBs which include a relatively large number of layers between signal paths which must be connected.
So-called micro-vias have also been proposed. Both the signal and density performance of micro-vias are very good in comparison to drilled vias. There are still discontinuities in the signal path, because the ground plane is disrupted. However, because the scale is so small, this problem is minimal, especially when only going through one layer (which does not break the continuous ground path). Micro-vias are particularly useful in applications in which the number of PCB layers is relatively small or where density is extreme, such as in micro ball grid array (&mgr;BGA) escapement. As an added benefit, micro-vias can be placed directly in a surface mount pad.
Because micro-vias must be manufactured from the outer surface (often out of non-woven aramid reinforced layers or unreinforced dielectric), the micro-vias can only be on the outer traces unless subsequent layers are built on top of the constructed panel. Each layer adds significant processing cost. Via depth is limited greatly because the plating chemistry cannot flow through small blind holes in the same manner as through-hole vias. Similar limitations exist for laser ablated and co-deposition vias. Thus, micro-vias are also not particularly useful in PCBs which include a relatively large number of layers between signal paths which must be connected.
Furthermore, none of the above techniques address the problem of maintaining signal strength and quality (i.e. shape of signal, lack of noise from either internal reflections or cross talk from other lines) collectively referred to herein as signal integrity as device operating frequencies increase and/or clock rise times decrease. Moreover, owing to the addition of noise as well as reflections due to impedance mismatches, signal quality suffers when the impedance of the layer-to-layer interconnection transmission structure changes, resulting in parasitic wave reflections and in some cases resonation. This results in a signal path having a relatively high insertion loss characteristic. A secondary related effect is crosstalk, which relates to the electromagnetic interference (EMI) between circuit structures. Thus, one problem with the prior art approaches, is that they merely attempt to increase density on a printed circuit board and they fail to provide any mechanisms for maintaining signal integrity and signal quality.
It would, therefore, be desirable to provide an interconnection structure which provides a layer-to-layer signal path which is relatively low loss, which does not degrade signal performance, which maintains signal integrity and which allows increased density of connections. It would also be desirable to provide an interconnection structure which is easily adapted to work with existing PCB manufacturing techniques, components and the like.
It would further be desirable to provide an interconnection structure which reduces the number and magnitude of impedance discontinuities due to transmission structure changes and which reduces the amount of crosstalk between circuit structures.
SUMMARY OF THE INVENTION
It has, in accordance with the present invention, been recognized that although signal lines within a single printed circuit board (PCB) layer are provided having predetermined impedance characteristics (i.e. the impedance of the signal line is controlled), such impedance control is not available for conventional plated-through holes (PTHs) which are used to provide signal paths between different layers of the PCB. This lack of control of the impedance characteristics of the via results in relatively la

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