Multi-comparison analog-to-digital converters using the interpol

Details Multi-comparison analog-to-digital converters using the interpol Multi-comparison analog-to-digital converters using the interpol

1995-07-18

1997-11-04

DeBoer, Todd E.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341122, 341136, H03M 136

Patent

active

056844859

ABSTRACT:
The disclosure concerns a so-called "auto-zeroing" comparator of two analog input voltages to be compared, and an analog-to-digital converter using a set of auto-zeroing comparators enabling the number of comparators required for an analog-to-digital conversion to be reduced. The main originality of the invention is that this comparator includes a second stage constituted by an inverter function provided in such a way that only a first transistor is controlled on its gate by the previous stage, a second transistor having its gate and drain short-circuited by a switch during the auto-zeroing phase, and a third transistor used as a capacitor and connected to the gate of said second transistor and also to the supply voltage. The present invention is applicable in particular to all types of CMOS multi-comparison ADCs using at least one "auto-zeroing" comparator.

REFERENCES:
patent: 4989003 (1991-01-01), Sauer
patent: 5302869 (1994-04-01), Hosotani et al.
patent: 5465093 (1995-11-01), Kusumoto et al.
Proceedings of the IEEE 1992 Integrated Circuits Conference, May 1992 New York, NY pp. 16.8.1-16.8.4 K.J. McCall et al. "A 6-bit 125 MHz CMOS A/D Converter".
IEEE 1993 WP4.3:A 106 20MHz 39m W Pipelined Interpolating CMOS ADC, K. Kusmoto, K. Murata, A. Matsuzawa, S. Tada, M. Maruyama, K. Oka, H. Konishi, Matsushita Electric Industrial Co. Ltd./Matsushita Electronics Corp., Osaka, Japan.

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