Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2007-10-09
2007-10-09
Lane, Jack (Department: 2185)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S189040, C711S005000
Reexamination Certificate
active
10955193
ABSTRACT:
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.
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Bellows Chad A.
Lai Lawrence
Richardson Wayne S.
Ware Frederick A.
Lane Jack
Rambus Inc.
Shemwell Mahamedi LLP
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