Multi-chips stacked package

Details Multi-chips stacked package Multi-chips stacked package

2007-09-11

2007-09-11

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000

Reexamination Certificate

active

10747128

ABSTRACT:
A multi-chips stacked package at least comprises a substrate, a lower chip, an upper chip, an adhesive layer, a supporting body and an encapsulation. The lower chip is disposed on the substrate and the upper chip is attached to the lower chip via the adhesive layer. In addition, the lower chip and the upper chip are electrically connected to the substrate via first electrically conductive wires and second electrically conductive wires respectively. Furthermore, the supporting body is disposed on the lower chip and at the periphery of the upper surface of the lower chip, and covered by the upper chip. The top of the supporting body is apart from the back surface of the upper chip with a distance. Accordingly, when the second electrically conductive wires are bonded the upper chip to the substrate with a larger bonding force to cause the upper chip to be tilted more, the supporting body will support the upper chip and prevent the upper chip from contacting the first electrically conductive wires.

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patent: 2003/0038374 (2003-02-01), Shim et al.

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