Multi-chips stacked package

Details Multi-chips stacked package Multi-chips stacked package

2007-05-08

2007-05-08

Vigushin, John B. (Department: 2841)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S723000, C257S778000, C257S784000, C361S767000, C361S783000

Reexamination Certificate

active

10747114

ABSTRACT:
A multi-chips stacked package mainly comprises a substrate, a first lower chip, a second lower chip, an upper chip and a carrier. The substrate has an upper surface, and the first lower chip and the second lower chip are disposed on the upper surface of the substrate and electrically connected to the substrate. The carrier is disposed on and electrically connected to the first lower chip and the second lower chip simultaneously, and the upper chip is mounted on the carrier. Moreover, the upper chip is electrically connected to the substrate through the carrier, the first lower chip or the second lower chip.

REFERENCES:
patent: 6319829 (2001-11-01), Pasco et al.
patent: 6351028 (2002-02-01), Akram
patent: 6407456 (2002-06-01), Ball
patent: 6555902 (2003-04-01), Lo et al.
patent: 6650006 (2003-11-01), Huang et al.
patent: 6861288 (2005-03-01), Shim et al.
patent: 2004/0238857 (2004-12-01), Beroz et al.

Affiliated with

Also associated with

Rating

Multi-chips stacked package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-chips stacked package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-chips stacked package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3726340