Multi-chips stacked package

Details Multi-chips stacked package Multi-chips stacked package

2006-02-21

2006-02-21

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S723000, C257S778000

Reexamination Certificate

active

07002255

ABSTRACT:
A multi-chips stacked package mainly comprises a substrate, a lower chip, an upper chip, an intermediate chip, a plurality of bumps and an encapsulation. Therein, the lower chip is disposed on the substrate; the bumps connect the lower chip and the intermediate chip; the upper chip and the lower chip are electrically connected to the substrate via a plurality of first electrically conductive wires and second electrically conductive wires respectively. The bumps can support the intermediate chip more firmly, so the top of the intermediate chip can be kept in counterpoise and higher than the peak of the first wires. Accordingly, the intermediate chip will be prevented from being tilted excessively to cause the upper chip to be contacted to the first electrically conductive wires. Thus, the first electrically conductive wires can be prevented from being damaged when the upper chip is wire bonded to the substrate.

REFERENCES:
patent: 5323060 (1994-06-01), Fogal et al.
patent: 5977640 (1999-11-01), Bertin et al.

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