Multi-chips stacked package

Details Multi-chips stacked package Multi-chips stacked package

2005-02-15

2005-02-15

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000, C257S778000, C257S784000

Reexamination Certificate

active

06856027

ABSTRACT:
A multi-chips stacked package at least comprises a substrate, an upper chip, a lower chip, a plurality of electrically conductive wires and a plurality of conductive bumps. The upper chip is flip-chip bonded to the upper surface of the substrate; and the lower chip is accommodated in the opening and wire-bonded to the upper chip. Furthermore, the lower chip can be wire-bonded to the substrate via a plurality of another electrically conductive wires, which directly connect the lower chip and the substrate.

REFERENCES:
patent: 6507098 (2003-01-01), Lo et al.
patent: 6507107 (2003-01-01), Vaiyapuri
patent: 6740973 (2004-05-01), Hsin

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