Multi-chip stacked package

Details Multi-chip stacked package Multi-chip stacked package

2009-04-27

2011-11-22

Smith, Zandra (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257SE23169

Reexamination Certificate

active

08063492

ABSTRACT:
A multi-chip stacked package primarily comprises a chip carrier, a first chip disposed on the chip carrier, a plurality of die-attaching bars, a second chip stacked on the first chip by the adhesion of the die-attaching bars, and a plurality of bonding wires electrically connecting the first chip to the chip carrier. The die-attaching bars are formed on the first chip in a specific pattern and have an adhesive surface away from the first chip for adhering the second chip. The bonding wires have a loop height lower than the adhesive surface in a manner that specific sections of the bonding wires are embedded in the corresponding die-attaching bar from the adhesive surface. Accordingly, the die-attaching bars can modify and fasten the bonding wires in advance to avoid collapse and deformation of the bonding wires during stacking of the second chip and encapsulating processes.

REFERENCES:
patent: 6683385 (2004-01-01), Tsai et al.
patent: 7298032 (2007-11-01), Kim et al.
patent: I250597 (2006-03-01), None

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