Multi-chip stack package and fabricating method thereof

Details Multi-chip stack package and fabricating method thereof Multi-chip stack package and fabricating method thereof

2007-03-21

2009-12-22

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S108000, C256S013000

Reexamination Certificate

active

07635610

ABSTRACT:
A multi-chip stack package includes a substrate, a first chip, a second chip, a plurality of bumps, a plurality of junction interface bumps, a plurality of conductive wires, a filler material and an encapsulating material. The substrate has a plurality of first contacts and a plurality of second contacts thereon. The first chip is bonded to the substrate surface by the bumps positioned between the active surface of the first chip and the first contacts. The second chip is bonded to the first chip by the junction interface bumps positioned between the back surface of the first chip and the back surface of the second chip. The conductive wires electrically connect the active surface of the second chip and the second contacts. The filler material encloses the bumps and the junction interface bumps. The encapsulating material encloses the first chip, the second chip and the conductive wires.

REFERENCES:
patent: 5726502 (1998-03-01), Beddingfield
patent: 6127724 (2000-10-01), DiStefano
patent: 6157080 (2000-12-01), Tamaki et al.
patent: 05-315540 (1993-11-01), None

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