Multi-chip stack package

Details Multi-chip stack package Multi-chip stack package

2007-05-15

2007-05-15

Smith, Zandra V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000, C257S781000, C257S784000

Reexamination Certificate

active

11258137

ABSTRACT:
A multi-chip stack package mainly includes a substrate, a first chip, a redistribution structure and at least one second chip. The first chip is disposed on the substrate with an active surface facing upwards. The redistribution structure includes a plurality of first intermediate pads, a plurality of second intermediate pads and a plurality of external pads. The first intermediate pads, the second intermediate pads, and the external pads are formed on the first active surface of the first chip, wherein the first intermediate pads and the second intermediate pads are electrically connected with each other. The second chip is disposed on the redistribution structure, and electrically connected to the first intermediate pads. The second intermediate pads are electrically connected to the substrate through a plurality of bonding wires, so that the second chip and the substrate are electrically conducted, and the connection length of the bonding wires is reduced.

REFERENCES:
patent: 6812575 (2004-11-01), Furusawa
patent: 6984889 (2006-01-01), Kimura
patent: 7084487 (2006-08-01), Conn
patent: 2003/0153122 (2003-08-01), Brooks

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