Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-09-30
2004-11-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S686000, C257S678000, C257S723000, C257S777000
Reexamination Certificate
active
06825064
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to multi-chip semiconductor packages, and more particularly, to a semiconductor package with a plurality of chips mounted on a chip carrier, and a fabrication method of the semiconductor package.
BACKGROUND OF THE INVENTION
In favor of effective enhancement in electrical and operational performances, it preferably incorporates more than one or a plurality of chips in a single package, thus forming a multi-chip semiconductor package. A conventional multi-chip semiconductor package
1
, as shown in
FIG. 3
, is a substrate-based structure, wherein a first chip
10
is mounted on a substrate
11
and electrically connected thereto by a plurality of first bonding wires
12
. A second chip
13
is stacked on the first chip
10
, and electrically connected to the substrate
11
by a plurality of second bonding wires
14
. An encapsulant
15
is formed on the substrate
11
, and encapsulates the first and second chips
10
,
13
and the first and second bonding wires
12
,
14
. A plurality of solder balls
16
are implanted on the substrate
11
opposed in position to the encapsulant
15
, and serve as input/output (I/O) ports for electrically connecting the first and second chips
10
,
13
to an external device such as a printed circuit board (PCB, not shown). However, this multi-chip semiconductor package
1
is subject to a chip-size limitation problem; that is, the second chip
13
should be smaller in dimension than the first chip
10
so as not to interfere with arrangement of the first bonding wires
12
bonded to the first chip
10
.
Accordingly, as shown in
FIGS. 4A and 4B
, another multi-chip semiconductor package
1
′ is provided for solving the above chip-size limitation problem, wherein the second chip
13
is stacked on the first chip
10
in a stagger manner, and thus partly in contact with the first chip
10
. By this arrangement, the second chip
13
may be flexibly sized with respect to the first chip
10
, and free of concern to interfere with the first bonding wires
12
connected to the first chip
10
. However, with partial or incomplete contact between the first and second chips
10
,
13
, the second chip
13
is formed with at least a suspending portion
130
that lacks support from the first chip
10
, with bond pads
131
of the second chip
13
, where the second bonding wires
14
are bonded, being situated at the suspending portion
130
. During a wire-bonding process for forming the second bonding wires
14
, a wire bonder (not shown) exerts a strong force toward the bond pads
131
, and thus may lead to cracks of the second chip
13
at the suspending portion
130
that is not supported by the first chip
10
.
In response to the above chip-crack problem, a further multi-chip semiconductor package
1
″, as shown in
FIG. 5
, teaches to form a plurality of support members
17
interposed between the suspending portion
130
and the substrate
11
. The support members
17
are situated substantially corresponding in position to the bond pads
131
of the second chip
13
where the second bonding wires
14
are bonded, and used to enhance mechanical strength or support for the second chip
13
and at the suspending portion
130
. As a result, the second chip
13
may become stronger against the wire-bonding force without easily cracking at the suspending portion
130
during formation of the second bonding wires
14
.
However, the above multi-chip semiconductor package
1
″ in the use of the support members
17
, induces significant problems. One is void or popcorn effect issues; the support members
17
are arranged to undesirably form gaps G between the first chip
10
and the support members
17
. During a molding process for forming the chip-encapsulation encapsulant
15
by a resin compound, the relative narrow gaps G would change motion of the resin compound passing therethrough and easily trap air or voids therein; this may lead to popcorn effect with voids left in the encapsulant
15
for the semiconductor package
1
″ in subsequent fabrication processes, and thereby adversely affect reliability of fabricated package products.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a multi-chip semiconductor package and a fabrication method thereof, which can prevent a chip accommodated in the semiconductor package from cracking during fabrication processes.
Another objective of the invention is to provide a multi-chip semiconductor package and a fabrication method thereof, wherein no gap is formed between a non-conductive material and a chip applied with the non-conductive material, such that no void or popcorn effect issue is generated.
A further objective of the invention is to provide a multi-chip semiconductor package and a fabrication method thereof, which can enhance mechanical strength for a chip and help minish thermal stress exerted to the chip, and also, the chip can be further thinned in favor of reducing overall package thickness.
A further objective of the invention is to provide a multi-chip semiconductor package and a fabrication method thereof, wherein a non-conductive material is applied over a chip and helps prevent external moisture from invading the chip, thereby assuring reliability of the semiconductor package.
In accordance with the above and other objectives, the present invention proposes a multi-chip semiconductor package, comprising: a substrate having an upper surface and a lower surface opposed to the upper surface; at least a first chip mounted on the upper surface of the substrate; a non-conductive material applied over predetermined area on the first chip and the upper surface of the substrate; at least a second chip mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material; and an encapsulant formed on the upper surface of the substrate for encapsulating the first and second chips.
A method for fabricating the above multi-chip semiconductor package comprises the steps of: preparing a substrate having an upper surface and a lower surface opposed to the upper surface; mounting at least a first chip on the upper surface of the substrate; applying a non-conductive material over predetermined area on the first chip and the upper surface of the substrate; mounting at least a second chip on the non-conductive material, wherein the second chip is formed with at least a suspending portion free of interference in position with the first chip, and the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material; and forming an encapsulant on the upper surface of the substrate for encapsulating the first and second chips.
The above semiconductor package provides significant benefits First, as the second chip is completely supported on the non-conductive material, during a wire-bonding process for forming the second bonding wires, the suspending portion of the second chip can be prevented from cracking in response to wire-bonding force exerted by a wire bonder, thereby assuring structural intactness of the second chip. Further, as the non-conductive material is directly applied over the first chip without forming gaps therebetween, no void or popcorn effect issue is concerned in this invention for fabricating the encapsulant. Moreover, the second chip is attached with one side thereof to the non-conductive material such as an elastic adhesive, and encapsulated with its opposed side by the encapsulant; this double-side encapsulation enhances mechanical strength and provides buffer effect for the second chip, and helps reduce thermal stress exerted to the second chip during subsequent high-temperature conditions, and also, the second chip
Chen Kuen-Huang
Hsu Yu-Ming
Lin Chin-Hsing
Su Wen-Sheng
Tsai Shiann-Tsong
Fulbright & Jaworski I
Nelms David
Tran Mai-Huong
UltraTera Corporation
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