Multi-chip semiconductor package

Details Multi-chip semiconductor package Multi-chip semiconductor package

2001-10-09

2002-12-17

Nguyen, Tuan H. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S666000, C257S670000, C438S111000

Reexamination Certificate

active

06495908

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to multi-chip semiconductor packages, and more particularly, to a multi-chip semiconductor package, in which two semiconductor chips are disposed in a staggered manner.
BACKGROUND OF THE INVENTION
A conventional semiconductor package generally includes a metal lead frame having a die pad and a plurality of leads, for disposing a semiconductor chip on the die pad and electrically connecting the chip to the corresponding leads by bonding wires. The chip, the die pad and part of the leads are encapsulated in an encapsulant, in an effort to protect the semiconductor package from damp, dust or damage.
However, in accordance with higher demand for operational function and speed of electronic products, more semiconductor devices are employed on a motherboard, or integrated circuits with higher integration level are utilized on a semiconductor chip. Nevertheless, the motherboard needs to expand its surface area for accommodating the larger number of the semiconductor devices, and this is undesirable in response to a trend for developing low-profile electronic products. Increase in integration level for the semiconductor chip is possibly limited by present manufacturing technology and is cost-ineffective to implement. Thus, an effective solution is to incorporate two or more chips in one semiconductor package, so as to raise the density of integrated circuits, the memory capacity and the process speed.
U.S. Pat. No. 5,898,220 discloses a multi-chip semiconductor package. Referring to
FIG. 1
, the semiconductor package includes a first semiconductor chip
11
, a second semiconductor chip
12
and a lead frame
10
. The first and second chips
11
,
12
each possesses a top surface
110
,
120
(where electric circuits and electronic components are disposed) and an opposing bottom surface
111
,
121
, respectively. On each of the top surfaces
110
,
120
there are formed two rows of bond pads
112
,
122
at two opposite sides. The lead frame
10
is composed of a plurality of leads
14
, wherein a surface of the leads
14
for mounting the first chip
11
thereon is referred to as a first surface
140
, while a surface of the leads
14
opposing the first surface
140
is referred to as a second surface
141
.
As shown in the drawing, a nonconductive first tape
150
is adhered to the first surface
140
of the leads
14
, and then the top surface
110
of the first chip
11
is firmly attached to the first tape
150
by using a conventional jig (not shown) under heat and pressure. Further, a plurality of gold wires
16
are used to electrically connect the bond pads
112
on the top surface
110
of the first chip
11
to the first surface
140
of the leads
14
. Similarly, the second chip
12
is attached to the second surface
141
of the leads
14
by means of a second tape
151
, and the bond pads
122
on the second chip are electrically connected to the second surface
141
of the leads
14
by a plurality of gold wires
16
. Finally, an encapsulant
17
is formed to encapsulate the first chip
11
, the second chip
12
, the gold wires
16
and a portion of the leads
14
close to the chips, so as to protect the semiconductor chips from outside moisture and pollutant.
In the use of the jig (as shown in
FIG. 2
by a reference numeral
18
), a heat source is provided for heating the tapes to firmly attach the semiconductor chips to the leads. However, as shown in
FIG. 2
, after completing the attachment of the first chip
11
, due to heat blockage by the first chip
11
and the highly heat-resistant first tape
150
, the second tape
150
receives heat in reduced transmission efficiency, and thus the second chip
12
is unable to be firmly bonded by means of the second tape
150
, resulting in increase in the reliability concern for die bonding. Moreover, in order to successively bonding the gold wires
16
to respectively the first chip II and the leads
14
, the second tape
151
needs to be dimensioned in thickness slightly larger than the height of wire loops of the gold wires
16
. In consideration of replacing the second tape
151
with a conventional nonconductive adhesive for improving the problem of poor beat transmission as described above, however, an adhesive layer formed by the adhesive with high fluidity is hardly controlled in thickness, and thus the gold wires
16
may suffer suppression from the second chip
12
, resulting in poor wire bonding quality.
In addition, in a molding process for the foregoing semiconductor package, as shown in
FIG. 3
, after a melted molding resin (not shown) is injected into a mold (not shown), a mold flow direction is perpendicular to gaps
142
between the leads
14
, which are interposed between the first and second chips
11
,
12
. This therefore makes the molding resin hardly flow into the gaps
142
, and the gaps
142
not completely filled with the molding resin easily have voids formed therein. Accordingly, a popcorn effect can be generated in the semiconductor package operating in a high temperature environment due to thermal expansion of air in the voids.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a multi-chip semiconductor package, in which chips are disposed in a staggered manner, so as to improve heat transmission efficiency of a jig in a die bonding process and thus maintain the die bonding reliability.
Another objective of the present invention is to provide a multi-chip semiconductor package, in which staggered chips allow a mold flow of a molding resin to be balanced and thus avoid void formation.
A further objective of the present invention is to provide a multi-chip semiconductor package, in which chips are simultaneously incorporated in lead-on-chip (LOC) and non-LOC manners.
A further objective of the present invention is to provide a multi-chip semiconductor package, in which chips are employed with no restriction on size.
A further objective of the present invention is to provide a multi-chip semiconductor package, in which no special jig is needed, and thus the fabrication cost is reduced.
According to the foregoing and other objectives, the present invention proposes a multi-chip semiconductor package, including: a lead frame having a front surface and an opposing back surface, and consisting of a die pad and a plurality of leads surrounding the die pad, wherein the die pad is firmly held at a position deviating from the center of the lead frame by a plurality of supporting elements; a first chip having an active surface and an opposing inactive surface, and bonded to the die pad on the front surface of the lead frame by means of an adhesive; a second chip having an active surface and an opposing inactive surface, wherein the active surface is attached to the supporting elements on the back surface of the lead frame and the leads formed around the supporting elements, so as to allow the first chip and the second chip to be spatially positioned in a staggered manner, a plurality of first conductive elements for electrically connecting the first chip to the leads; a plurality of second conductive elements for electrically connecting the second chip to the leads; and an encapsulant for encapsulating the first chip, the second chip, the first conductive elements, the second conductive elements and part of the leads.
The semiconductor package of the invention is advantageous in that at least two semiconductor chips are incorporated in the same package simultaneously, and the first and second chips are respectively attached to the front and back surfaces of the lead frame in a staggered manner. This staggered arrangement makes die bonding processes performed for the first and second chips without interfering with each other, so that the second chip can be firmly disposed in the semiconductor package. This is more advantageous than the prior art, in which bonding quality of a second chip is detrimentally affected due to heat transmission blocked by a first chip located vertically with respect to the second chip. As a

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