Multi-chip semiconductor package

Details Multi-chip semiconductor package Multi-chip semiconductor package

1999-10-07

2001-11-13

Wong, Peter S. (Department: 2838)

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

C257S686000

Reexamination Certificate

active

06316727

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor package. More particularly, the present invention relates to a multi-chip semiconductor package.
2. Description of Related Art
In the semiconductor industry, the fabrication of integrated circuits is divided into three stages: the fabrication of wafers, the formation of integrated circuits, and the packaging of integrated circuits. The purpose of the packaging is to provide electrical connection between dies and a printed circuit board or other desired devices, as well as protection.
After the formation of integrated circuits, a wafer is cut into dies. In general, the dies have bonding pads thereon to provide die testing points, and to provide connection between the dies and other devices. In general, wires and bumps are provided to connect the dies and other devices.
FIG. 1
is a schematic, cross-sectional diagram of a conventional semiconductor package.
Referring to
FIG. 1
, a chip
100
is attached to a die pad
102
, which is in the center region of a lead frame
104
. Bonding pads
106
made of metal are mounted in one surface of the chip
100
. The bonding pads
106
are used for coupling with other devices, and are typically made of aluminum. The surface of the chip
100
without bonding pads is fixed to the die pad
102
by an adhesive. After the chip
100
is fixed, each bonding pad
106
in the bonding pad surface of the chip
100
is coupled to each corresponding lead
110
by wires
108
. The chip
100
, wires
108
, and a portion of the leads
110
are sealed in packaging material
112
. The packaging material
112
fixes devices in their required positions and protects the chips
100
and the connection points of the chip
100
and the wires
108
, and also prevents moisture from penetrating into the packaging. An exposed portion of the leads
110
is bent downward for coupling to a printed circuit board (not shown).
Increasing integration in integrated circuits creates increased requirements for packages. However, only one chip is packaged in a conventional package. Integration and performance are limited by only one chip in the conventional package so that the integration of devices and performance cannot be enhanced, and capital expenditure cannot be lowered. Therefore, it is important for the packaging industry to increase device integration and performance, and to further lower the capital expenditure.
SUMMARY OF THE INVENTION
The invention provides a multi-chip semiconductor package. The multi-chip package comprises a first chip, a second chip, a lead frame, a plurality of wires, and a packaging material. The first chip has a first surface and a second surface, and the first surface has a plurality of first bonding pads. The second chip has a third surface and a fourth surface, and the third surface has a plurality of second bonding pads. The lead frame comprises a die pad and a plurality of leads. The die pad has a fifth surface and a sixth surface, wherein the fifth surface is attached to the second surface and the sixth surface is attached to the third surface, and the die pad has an area smaller than that of the second chip so as to expose the second pads. The leads have an inner portion and an outer portion. The plurality of wires respectively couple the first bonding pads and the second bonding pads to the inner portion of the leads. The first chip, the second chip, and the inner portion of the leads are all sealed within the packaging material.
As embodied and broadly described herein, the invention provides a multi-chip semiconductor package, whose manufacturing method is easily combined with current package technology.
The invention changes the design for a lead frame by using a die pad whose surface area is smaller than that of a chip. Thus, chips do not need any additional treatment. Therefore, chips with the same layout can be used and manufacturing cost is low.
In the invention, more than two chips are packaged together. When this structure is employed in DRAM, the memory density is increased. Thus, device integration is increased, and performance is enhanced without re-designing and re-manufacturing chips. Therefore, the package described in the invention can be rapidly introduced to the market. Due to a decrease in the distance between devices, transmission speed is increased, and device performance is also enhanced.
The package in the invention can increase density and performance of chips and device integration without increasing capital expenditure.
The invention can be employed in a logic device; thus, chips with different functions are packaged together. Therefore, the functions of a package are increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5422435 (1995-06-01), Takiar et al.

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