Multi-chip semiconductor package

Details Multi-chip semiconductor package Multi-chip semiconductor package

1992-04-10

1994-07-19

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

257723, H01L 2316

Patent

active

053312350

ABSTRACT:
A Multi-chip semiconductor package having the thinnest structure. The package includes a chip set including a first bare chip and a second bare chip which are connected to each other by solder interposed therebetween and a plurality of TAB tapes each having an inner lead and an outer lead, the first bare chip and the second bare chip being provided with a plurality of solder bumps at opposite sides of surfaces thereof facing to each other, each of the inner leads being bonded between each corresponding the solder bump of the first bare chip and each corresponding the solder bump of the second bare chip, and a lead frame bonded to the outer leads of the TAB tapes. The chip set of the multi-chip semiconductor package may be connected to other chip set so that the package has four bare chips. Therefore, the thinnest multi-chip semiconductor package can be achieved and an integration of the package is improved. Also, a chip set is formed by fixing lead frames between two bare chips, to render the chip sets stably and firmly stacked and the pads of each bare chip disposed at desired position.

REFERENCES:
patent: 4862322 (1989-08-01), Bickford et al.
patent: 4982265 (1991-01-01), Watanabe et al.
patent: 5010387 (1991-04-01), Dunaway et al.
"Development of Packages for Memory Which Enables to Enlarge the Capacity of 2-4 Times the Same Sizes as TSOP and SOJ", (Reliability is equal to the Conventional Package), Nikkei Micro Denies p. 80, Apr. 1991.

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