Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-06-27
2002-04-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000, C438S109000, C438S113000, C438S123000, C438S127000
Reexamination Certificate
active
06368894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-chip semiconductor module and a manufacturing process thereof. More particularly, the present invention relates to a multi-chip semiconductor module manufacturing process for increasing the yield of the multi-chip semiconductor module, and a multi-chip semiconductor module that incorporates different functional chips.
2. Description of the Prior Art
Portability is a main development trend in the semiconductor industry. In order to reduce the overall size and weight of an electronic product, the size of a printed circuit board has to be reduced first. It has been proposed to combine semiconductor chips with different functions into a single semiconductor module, that is, the multi-chip semiconductor module.
However, poor yield of the multi-chip semiconductor module has always been a problem during mass production. When one of the semiconductor chips in the module is defective, the whole module will be affected.
Accordingly, the present invention is directed to a multi-chip semiconductor module manufacturing process for increasing the yield of the multi-chip semiconductor module, and a multi-chip semiconductor module that incorporates semiconductor chips with different functions.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a process of manufacturing a multi-chip semiconductor module comprises the steps of: (a) providing a substrate having opposite first and second surfaces, a plurality of conductive vias that extend through the first and second surfaces, a circuit layout patterned on the first surface of the substrate and connected electrically to the conductive vias, and a chip-receiving opening formed therein; (b) mounting a contact pad surface of a first semiconductor chip on the first surface of the substrate such that the first semiconductor chip has a first set of contact pads registered with the chip-receiving opening, and a second set of contact pads around the chip-receiving opening, and connecting electrically the second set of contact pads of the first semiconductor chip to the circuit layout; (c) disposing an adhesive layer having opposite first and second adhesive surfaces and a plurality of windows that extend through the first and second adhesive surfaces inside the chip-receiving opening, and adhering the second adhesive surface of the adhesive layer to the contact pad surface of the first semiconductor chip such that the windows are registered with the first set of contact pads of the first semiconductor chip; (d) placing a conductive body in each of the windows; and (e) disposing a second semiconductor chip in the chip-receiving opening, and attaching a contact pad surface of the second semiconductor chip to the first adhesive surface of the adhesive layer so that a plurality of contact pads on the contact pad surface of the second semiconductor chip are connected electrically and respectively with the conductive bodies in the windows to establish electrical connection with the first semiconductor chip.
In another aspect of the present invention, a process of manufacturing a multi-chip semiconductor module comprises the steps of: (a) providing a substrate having opposite first and second surfaces, a plurality of conductive vias that extend through the first and second surfaces, first and second circuit layouts patterned respectively on the first and second surfaces of the substrate and connected electrically to the conductive vias, and a chip-receiving opening formed therein; (b) mounting a contact pad surface of a first semiconductor chip on the first surface of the substrate such that the first semiconductor chip has a first set of contact pads registered with the chip-receiving opening, and a second set of contact pads around the chip-receiving opening, and connecting electrically the second set of contact pads of the first semiconductor chip to the first circuit layout; (c) disposing a second semiconductor chip in the chip-receiving opening, mounting a contact pad surface of the second semiconductor chip to the contact pad surface of the first semiconductor chip, and connecting electrically a plurality of contact pads on the contact pad surface of the second semiconductor chip with the first set of contact pads of the first semiconductor chip; and (d) mounting a contact pad surface of a third semiconductor chip on the second surface of the substrate, and connecting electrically a plurality of contact pads on the contact pad surface of the third semiconductor chip to the second circuit layout.
In still another aspect of the present invention, a multi-chip semiconductor comprises: a substrate having opposite first and second surfaces, a plurality of conductive vias that extend through the first and second surfaces, a circuit layout patterned on the first surface of the substrate and connected electrically to the conductive vias, and a chip-receiving opening formed therein; a first semiconductor chip having a contact pad surface on which first and second sets of contact pads are disposed; a first adhesive layer having a first adhesive surface adhered to the first surface of the substrate and a second adhesive surface adhered to the contact pad surface of the first semiconductor chip such that the first set of contact pads is registered with the chip-receiving opening, and such that the second set of contact pads is disposed around the chip-receiving opening, the first adhesive layer being formed with a plurality of windows that extend through the first and second adhesive surfaces and that are registered with the second set of contact pads; a plurality of conductive bodies disposed respectively in the windows of the first adhesive layer and connecting electrically the second set of contact pads and the circuit layout; a second adhesive layer disposed inside the chip-receiving opening and having opposite first and second adhesive surfaces and a plurality of windows that extend through the first and second adhesive surfaces of the second adhesive layer, the second adhesive surface of the second adhesive layer being adhered to the contact pad surface of the first semiconductor chip such that the windows of the second adhesive layer are registered with the first set of contact pads of the first semiconductor chip; a plurality of conductive bodies disposed respectively in the windows of the second adhesive layer and connected electrically to the first set of contact pads; and a second semiconductor chip disposed in the chip-receiving opening and having a contact pad surface attached to the first adhesive surface of the second adhesive layer, the contact pad surface of the second semiconductor chip having a plurality of contact pads that are connected electrically and respectively with the conductive bodies in the windows of the second adhesive layer to establish electrical connection with the first semiconductor chip.
In yet another aspect of the present invention, a multi-chip semiconductor module comprises: a substrate having opposite first and second surfaces, a plurality of conductive vias that extend through the first and second surfaces, first and second circuit layouts patterned respectively on the first and second surfaces of the substrate and connected electrically to the conductive vias, and a chip-receiving opening formed therein; a first semiconductor chip having a contact pad surface on which first and second sets of contact pads are disposed, the contact pad surface of the first semiconductor chip being mounted on the first surface of the substrate such that the first set of contact pads are registered with the chip-receiving opening, and such that the second set of contact pads are disposed around the chip-receiving opening and are connected electrically to the first circuit layout; a second semiconductor chip disposed in the chip-receiving opening, and having a contact pad surface on which a plurality of contact pads are disposed, the contact pad surface of the second semiconductor chip being mounted to the contact pad surface of the
Anya Igwe U.
Merchant & Gould P.C.
Smith Matthew
LandOfFree
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