Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-03-16
2004-01-06
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S682000, C257S704000, C257S712000
Reexamination Certificate
active
06674160
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device capable of being integrated more highly than a conventional one and a method of fabricating such a semiconductor device.
2. Description of the Related Art
A conventional semiconductor device is generally designed to include a plurality of semiconductor chips two-dimensionally arranged on a substrate.
FIG. 1
is a side view illustrating such a conventional semiconductor device.
The illustrated semiconductor device is comprised of a substrate
20
on which wirings are formed in a predetermined pattern, TAB (Tape Automated Bonding) tapes
25
on each of which a first LSI chip
40
A and a second LSI chip
40
B is mounted, respectively, bonding wires BW electrically connecting bonding pads of the first and second LSI chips
40
A and
40
B to electrically conductive leads of TAB tapes
25
, resin
26
covering the first and second LSI chips
40
A and
40
B and the bonding wires BW on the TAB tapes
25
, and solder balls
29
electrically connecting the TAB tapes
25
to the substrate
20
.
The above-mentioned conventional semiconductor device attempts to achieve higher integration by two-dimensionally arranging a plurality of LSI chips. However, since the substrate
20
has a limited size, it would be impossible to much increase the number of LSI chips to be arranged on the substrate
20
, resulting in difficulty in higher integration of LSI chips.
To solve this problem, Japanese Unexamined Patent Publications Nos. 10-84076, 8-32183 and 9-8220 have suggested a semiconductor device for achieving higher integration.
For instance, the semiconductor device suggested in Japanese Unexamined Patent Publication No. 10-84076 is designed to include a first package in which a first LSI chip is sealed, and a second package in which a second LSI chip is sealed and which is vertically stacked on the first package. The first and second LSI chips are electrically connected to a substrate through ball grid arrays (BGA) and electrically conductive leads of an auxiliary substrate.
However, the above-mentioned semiconductor device suggested in Japanese Unexamined Patent Publication No. 10-84076 is accompanied with the following problem. Since the above-mentioned semiconductor device is intended to be as small as possible in size, a gap between the first and second LSI chips is quite small. In addition, the gap is filled with resin. As a result, path through which heat generated in the second or upper LSI chip is radiated is not sufficiently ensured, resulting in that heat generated in the second or upper LSI chip is transferred to the first or lower LSI chip through the resin filling the gap therewith. The thus transferred heat prevents proper operation of the first or lower LSI chip.
SUMMARY OF THE INVENTION
In view of the above-mentioned problem of the conventional semiconductor device, it is an object of the present invention to provide a semiconductor device which is capable of preventing heat generated in an upper semiconductor chip from transferring to a lower semiconductor chip.
It is also an object of the present invention to provide a method of fabricating such a semiconductor device.
In one aspect of the present invention, there is provided a semiconductor device including (a) a package defining a closed adiabatic space therein, (b) a first semiconductor chip arranged in the closed adiabatic space, and (c) a second semiconductor chip mounted on the package.
There is further provided a semiconductor device including (a) a package comprised of a base, a sidewall standing on the base at a periphery of the base, and a cover mounted over the sidewall, the base, sidewall and cover defining a closed adiabatic space in the package, (b) a first semiconductor chip mounted on the base in the close adiabatic space, and (c) a second semiconductor chip mounted on the cover.
In accordance with the above-mentioned semiconductor device, semiconductor chips can be highly integrated by vertically arranging them, and in addition, the closed adiabatic space formed between the first and second semiconductor chips solves the problem that heat generated in the second semiconductor chip is transferred to the first semiconductor chip, ensuring proper operation of the first semiconductor chip.
In a preferred embodiment, each of the base and the cover is comprised of a printed wiring board.
In accordance with the embodiment, signals transmitted from the first and second semiconductor chips can be readily transmitted outside the package.
In a preferred embodiment, the cover is comprised of a metal plate.
In accordance with the embodiment, it would be possible to enhance heat-radiation characteristic of the second semiconductor chip mounted on the cover.
In a preferred embodiment, when the base is formed therein with a first wiring terminal appearing at an upper surface of the base, and the sidewall is formed therein with a second wiring terminal appearing at a lower surface of the sidewall, the semiconductor device further includes a solder ball located between the base and the sidewall, the first and second wiring terminals being electrically connected to each other through the solder ball.
In accordance with the embodiment, it would be possible to surely electrically connect the base to the sidewall.
In a preferred embodiment, when the sidewall is formed therein with a wiring terminal appearing at an upper surface of the sidewall, the semiconductor device further includes a bonding wire through which the second semiconductor chip is electrically connected to the wiring terminal. The bonding wire may be covered with resin on the cover.
In a preferred embodiment, when the base is formed therein with a wiring terminal appearing at an upper surface of the base, the semiconductor device further includes a bonding wire through which the first semiconductor chip is electrically connected to the wiring terminal. The bonding wire may be bent in the closed adiabatic space.
In another aspect of the present invention, there is provided a semiconductor device including (a) a plurality of packages vertically stacked one on another, each of the packages defining a closed adiabatic space therein, and (b) a plurality of semiconductor chips each arranged in the closed adiabatic space of each of the packages.
There is further provided a semiconductor device including (a) a plurality of packages vertically stacked one on another, each of the packages being comprised of a base, a sidewall standing on the base at a periphery of the base, and a cover mounted over the sidewall, the base, sidewall and cover defining a closed adiabatic space in each of the packages, and (b) a plurality of semiconductor chips each arranged in the closed adiabatic space of each of the packages.
In a preferred embodiment, when the base is formed therein with a first wiring terminal appearing at an upper surface of the base, and the sidewall is formed therein with a second wiring terminal appearing at a lower surface of the sidewall, the semiconductor device further includes solder balls each located between the base and the sidewall, the first and second wiring terminals being electrically connected to each other through each of the solder balls.
In a preferred embodiment, when the sidewall is formed therein with a wiring terminal appearing at an upper surface of the sidewall, the semiconductor device further includes bonding wires through each of which a semiconductor chip mounted on a package which the sidewall partially constitutes is electrically connected to the wiring terminal.
In a preferred embodiment, when the base is formed therein with a wiring terminal appearing at an upper surface of the base, the semiconductor device further includes a bonding wire through which a semiconductor chip mounted in a package which the base partially constitutes is electrically connected to the wiring terminal.
In another aspect of the present invention, there is provided a method of fa
Andújar Leonardo
Flynn Nathan J.
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
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