Multi-chip packaging using an interposer with through-vias

Details Multi-chip packaging using an interposer with through-vias Multi-chip packaging using an interposer with through-vias

2007-05-30

2010-11-30

Nguyen, Donghai D. (Department: 3729)

Metal working

Method of mechanical manufacture

Electrical device making

C029S831000, C029S832000, C029S840000, C174S262000, C438S459000

Reexamination Certificate

active

07841080

ABSTRACT:
One embodiment relates to forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. A plurality of electronic elements are coupled to the second metal pads. After the coupling the elements, the body is thinned through a lower surface. A portion of the insulating layer in the vias is removed and the electrically conductive layer is coupled to a substrate.

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