Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
1999-10-13
2003-01-14
Jackson, Jerome (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S707000, C257S723000, C257S724000, C257S777000
Reexamination Certificate
active
06507098
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-chip packaging structure. More particularly, the present invention relates to a multi-chip packaging structure with enhanced integration level and heat dissipation performance.
2. Description of the Related Art
High performance, high integration level, low cost, and increased miniaturization of components for electronic products have long been the goals of manufacturing design. For semiconductor fabrication, mass production of 0.18 microns structure has already begun and its integration level need not be emphasized. However, the integration level of packaging is mainly determined in terms of the densification of the carriers and the spaces used for connections between the chips and the carriers.
Lead-over-chip (LOC) arrangement is a typical packaging structure employed to reduce the spaces used for connections between the chips and the carriers. Generally speaking, such arrangement includes a lead frame with a plurality of lead fingers extended to the center bonding pads of the chip and attached to the active surface of the chip. Moreover, the lead fingers also provide physical support for the chip. Thus, this arrangement can reduce the overall volume of the package. Therein, the carriers used include typical LOC lead frames, or laminated substrates with openings or slots.
In addition, a multichip module (MCM) arrangement is also a typical high integration level packaging structure. The MCM constitutes the encapsulation of a plurality of semiconductor chips on a single carrier which is usually called a laminated substrate. These chips include microprocessors, DRAMs, SRAMs, Flash memories and so on. Encapsulation of them not only reduces the volume of the package but also increases the performance by shortening the connection paths among chips.
Currently, a MCM is usually affixed to a printed circuit board (PCB) with a plurality of chips positioned on the same surface of the PCB. Connections to the PCB include wire bonding, tape automatic bonding (TAB), or flip-chip bonding. However, as known in the art, a MCM mainly aligns the chips to the same surface of the PCB. This arrangement occupies a relatively large area. Furthermore, the connection paths among chips are by means of complicated routes inside the PCB. Thus, the length and the resistance of the paths are both increased. Hence, the overall performance of the package is reduced.
In addition, as a plurality of chips is operated in a relatively small area in a multi-chip package, a considerably large amount of heat is generated. How to effectively dissipate the generated heat, which affects the performance of a multi-chip package, is currently of great concern to industry.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a multi-chip packaging structure in which the signal paths between chips can be reduced, and hence, the overall performance can then be increased.
Another object of the present invention is to provide a multi-chip packaging structure in which the overall volume of the package can be reduced, and hence, the integration level of the package can then be increased.
Yet another object of the present invention is to provide a multi-chip packaging structure in which the heat dissipation performance of the package can be improved.
Still another object of the present invention is to provide a multi-chip ball grid array packaging structure in which the volume of the package can be reduced, the package integration level is increased, and the connection paths among chips is shortened so that the overall performance is increased. Also, the heat dissipation performance of the package can be improved.
These objects of the present invention have been achieved by introducing a multi-chip ball grid array packaging structure. The structure at least comprises a substrate, a first chip, a second chip, and a heat sink. The substrate has a first surface and a second surface, and an opening passing through the first surface and the second surface. It also includes a plurality of conductive areas located on the first surface, with at least one of the conductive areas lying laterally adjacent to the perimeter of the opening. The first chip includes a first active surface and a first back surface, with a plurality of first bonding pads located on the first active surface. The first chip is arranged with the first active surface facing the second surface and secured on it such that the first bonding pads are exposed by the opening. The first bonding pads are electrically connected to the conductive areas lying laterally adjacent to the opening by bonding wires extending through the opening. The second chip includes a second active surface and a second back surface, with a plurality of second bonding pads located on the second active surface. The second chip is secured on the first surface of the substrate with the second bonding pads of the second chip electrically connected to the conductive areas of the substrate. A heat sink is located on the first back surface of the first chip and is thermally coupled with the first chip.
In a preferred embodiment according to the present invention, the structure described above can be positioned on laminated substrates for ball grid array assemblies. Then, a plurality of solder ball pads are also included on the second surface of the substrate with solder balls placed on them. The second chip is electrically connected to the conductive areas of the substrate by means of wire bonding or flip-chip bonding. When the center bonding pads arrangement is used in the first chip, the path of signal transmission between the first and the second chips can be reduced, and hence, the performance is increased. Also, the first chip and the second chips are separately located on the two surfaces of the substrate so that the area and the volume of the package can be reduced. A recess sized and shaped to receive the first chip can be defined on the second surface of the substrate; thus, the size of the package is further reduced. By means of the arrangement of the heat sink, the heat generated from the chips can be dissipated through the solder balls and the heat sink. Hence, the heat dissipation performance of the package is enhanced. Moreover, since the heat sink and the solder balls have been aligned on the same side, the heat sink can then be connected to the PCB by an adhesive. This allows the heat to be dissipated to the PCB, and hence, further improves the heat dissipation performance.
REFERENCES:
patent: 5903052 (1999-05-01), Chen et al.
patent: 6104089 (2000-08-01), Akram
patent: 6184580 (2001-02-01), Lin
Lo Randy H. Y.
Wu Chi-Chuan
J.C. Patents
Jackson Jerome
Rao Shrinivas H.
Siliconware Precision Industries Co. Ltd.
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