Multi-chip package with stacked chips and interconnect bumps

Details Multi-chip package with stacked chips and interconnect bumps Multi-chip package with stacked chips and interconnect bumps

1998-12-08

2000-12-12

Gaffin, Jeffrey

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361761, 361764, 361767, 361777, 257686, 257723, 257777, 365 51, H05K 118, H05K 706

Patent

active

061607185

ABSTRACT:
A multi-chip package includes a substrate having an opening about the central region. At least two integrated circuit chips are mounted on the substrate. The first chip is connected to one side of the substrate, while the second chip is connected to the other side of the substrate. At least a portion of one of the chips is positioned within the opening, and the chips are vertically stacked. The bottom side of the substrate includes a plurality of interconnect bumps for providing electrical connection to a circuit board or other substrate.

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