Multi-chip package substrate for flip-chip and wire bonding

Details Multi-chip package substrate for flip-chip and wire bonding Multi-chip package substrate for flip-chip and wire bonding

2006-10-24

2006-10-24

Potter, Roy (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S613000, C438S508000

Reexamination Certificate

active

07125745

ABSTRACT:
A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

REFERENCES:
patent: 6157080 (2000-12-01), Tamaki et al.
patent: 6353263 (2002-03-01), Dotta et al.
patent: 6777796 (2004-08-01), Fujimoto et al.
patent: 6781221 (2004-08-01), Yoneda
patent: TW515061 (2002-12-01), None

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