Multi-chip package structure and method of fabricating the same

Details Multi-chip package structure and method of fabricating the same Multi-chip package structure and method of fabricating the same

2011-06-28

2011-06-28

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S678000, C257S688000, C257S691000, C257S696000, C257S758000

Reexamination Certificate

active

07968992

ABSTRACT:
A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to a cut cross-section of the first metal layer exposed by the cavities. In addition, conductive bumps of a second wafer are pressed into a cover layer and electrically connected to the first circuit layer. The first metal layer is then patterned to form a second circuit layer having a number of second pads. Next, the first wafer and the second wafer are cut along the predetermined cutting line to form a number of separated multi-chip package structures.

REFERENCES:
patent: 6506633 (2003-01-01), Cheng et al.
patent: 6876074 (2005-04-01), Kim
patent: 6998704 (2006-02-01), Yamazaki et al.
patent: 2002/0046880 (2002-04-01), Takubo et al.
patent: 2005/0046002 (2005-03-01), Lee et al.
patent: 2006/0046432 (2006-03-01), Sankarapillai et al.

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