Multi-chip package and method for manufacturing the same

Details Multi-chip package and method for manufacturing the same Multi-chip package and method for manufacturing the same

2008-05-06

2008-05-06

Cao, Phat X (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000, C257SE23085, C438S109000

Reexamination Certificate

active

07368811

ABSTRACT:
A multi-chip package and method for manufacturing are disclosed. The multi-chip package may include a substrate, a lower semiconductor chip mounted on the substrate, a first electrical connection for electrically connecting the substrate and the lower semiconductor chip, an upper semiconductor chip attached to the lower semiconductor chip and having overhang portions, and at least one bump interposed between the substrate and the overhang portions. The at least one bump may support the overhang portions and may be formed when the first electrical connection is formed.

REFERENCES:
patent: 5721452 (1998-02-01), Fogal et al.
patent: 6337226 (2002-01-01), Symons
patent: 6664643 (2003-12-01), Emoto
patent: 7166924 (2007-01-01), Lu et al.
patent: 2002/0125556 (2002-09-01), Oh et al.
patent: 2004/0262774 (2004-12-01), Kang et al.
patent: 07-221262 (1995-08-01), None
patent: 2001-320014 (2001-11-01), None
patent: 10-0393094 (2003-07-01), None
Korean Patent Office Action dated Jan. 13, 2006.

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