Multi-chip package

Details Multi-chip package Multi-chip package

2008-04-22

2008-04-22

Dinh, Tuan T. (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C365S233100, C365S200000, C257S723000

Reexamination Certificate

active

07362587

ABSTRACT:
A multi-chip package includes a first semiconductor memory controlled by a clock signal and an inverted clock signal, and a second semiconductor memory controlled by the clock signal. The first semiconductor memory and the second semiconductor memory each include a circuit for guaranteeing that a signal delay is suppressed between a peripheral circuit, and a pad to which the clock signal is input, a pad to which the inverted clock signal is input, a pad for outputting a data enable signal and a pad for outputting a data signal. Thus, it is guaranteed that the signal delay is suppressed, and the reliability of the multi-chip package is improved.

REFERENCES:
patent: 5475646 (1995-12-01), Ogihara
patent: 6873563 (2005-03-01), Suwa et al.
patent: 7017068 (2006-03-01), McBride et al.
patent: 7149135 (2006-12-01), Okuno
patent: 6-274241 (1994-09-01), None
patent: 11-31747 (1999-02-01), None
patent: 11-102969 (1999-04-01), None
patent: 2005-135183 (2005-05-01), None

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