Multi chip package

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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Details

C257S686000, C257S777000, C257S784000, C257SE23025

Reexamination Certificate

active

10985020

ABSTRACT:
A multi chip package includes a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted above the first semiconductor chip; a first bonding wire electrically coupled to a first bonding pad on the first semiconductor chip; and a second bonding wire electrically coupled to a second bonding pad on the second semiconductor chip. At least the first bonding wire is of a coated wire, which comprises a conductive core and an outer insulation coating. At least the first bonding pad is of a multi layered pad, comprising a base pad formed on the first semiconductor chip; a first conductive layer formed on the base pad; and a second conductive layer formed on the first conductive layer.

REFERENCES:
patent: 5933712 (1999-08-01), Bernhardt et al.
patent: 5990500 (1999-11-01), Okazaki
patent: 6137185 (2000-10-01), Ishino et al.
patent: 6175153 (2001-01-01), Yamada
patent: 6710455 (2004-03-01), Goller et al.
patent: 6930396 (2005-08-01), Kurita et al.
patent: 2002/0030262 (2002-03-01), Akram
patent: 2003/0080428 (2003-05-01), Izumitani et al.
patent: 2003/0214795 (2003-11-01), Sakuyama
patent: 2004/0026781 (2004-02-01), Nakai
patent: 2004/0119172 (2004-06-01), Downey et al.
patent: 2000-068322 (2000-03-01), None

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