Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2000-02-10
2002-12-17
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S706000, C257S707000, C257S708000, C257S711000, C257S733000
Reexamination Certificate
active
06495914
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a multi-chip module structure having a plurality of bare semiconductor chips and at least one conductive post mounted on a base substrate, and a fabrication method thereof.
As a means for making electronic devices small and of high performance, there is known the so-called multi-chip module in which a plurality of bare semiconductor chips and passive elements are interconnected to form one module.
One example of the conventional methods of mounting a bare semiconductor chip is disclosed in JP-A-3-155144 (laid open Jul. 3, 1991). In this example, a hole larger than the semiconductor IC chip in a predetermined degree is previously formed in an insulating film that is thicker than the bare semiconductor chips in a predetermined degree. This insulating film is stuck to a support plate with an adhesive, and the bare semiconductor IC chip is bonded with an adhesive into the hole in the insulating film. A liquid resin resin of the same material as that of the insulating film is applied to gaps between the insulating film and the bare semiconductor IC chips and to the surface of the bare semiconductor IC chip so that the surface of the insulating film layer has a uniform level over the support plate. This applied resin is heated to cure, and the resin on the pads of the bare semiconductor IC chips is removed by photolithography. Then, a conductive film is deposited over the entire surfaces, and patterned by photolithography to form predetermined conductor wiring patterns.
One example of the conventional semiconductor devices (particularly multi-chip modules) and fabrication methods thereof is disclosed in JP-A-5-47856 (laid open Feb. 26, 1993). In this example, a chip is mounted on at least one stage provided on a package, and an insulating film is coated on the package and the chips. Via-holes are provided in the insulating film in order to connect the connection pads on the package and the pads on the chips. These via holes are connected by a wiring conductor pattern.
In the examples of JP-A-3-155144 and JP-A-547856, the support plate or package is an insulating substrate, and the material of the insulating substrate is generally one order of magnitude or more lower in thermal conductivity than the conductive and semiconductor materials. Thus, these examples are not suited for mounting large-power consumption chips such as power amplifiers.
Moreover, in the example of JP-A-5-47856, the mounting conductive layers (for example, Au-Si eutectic or conductive adhesive) on the rear sides of the chips do not have electrical junctions with the wiring conductors on the insulating film.
Also, in the example of JP-A-3-155144 of the conventional bare semiconductor chip mounting methods, when the same liquid resin as the material of the insulating film is filled in the gaps between the insulating film and the bare semiconductor IC chips and coated on the surfaces of the bare semiconductor IC chips so that the coated liquid resin surface can have a uniform level over the support plate, and when the liquid resin is heated to cure, depressions may be formed, due to the contraction of the resin, in the surfaces of the cured resin filed in the gaps between the insulating film and the bare semiconductor IC chips. The occurrence of depressions in the gaps will sometimes cause short circuits or disconnection in the wiring conductors on the gaps.
Even in the example of JP-A-5-47856 of the semiconductor devices and fabrication methods thereof, when the liquid resin is heated to cure, depressions may be sometimes caused in the insulating film across the gaps between the package and the chips due to the contraction of the resin. The depressions may cause short circuits or disconnection in the wiring conductors across the gaps.
As a means for solving this problem, there is known a chip-buried type multi-chip module. In this method, a plurality of projections or recesses are previously provided on a metal base substrate, and bare semiconductor chips are placed in the recesses and covered with an insulating resin film so that the bare chips can be buried. The insulating film is flattened by grinding or the like so that the insulating film can be made flush with the bump electrodes on the bare semiconductor chips. Then, thin film passive components, metal layers and insulating films are mounted and deposited on the base substrate to form a multilayered structure. In this method, however, desired projections or recesses cannot be easily formed on the base substrate.
In addition, the conventional examples are constructed not to enable a cap to be mounted on each multi-chip module structure. Therefore, the conventional structures cannot be mechanically protected from the damage from the outside, and thus they are easy to be broken. Moreover, when operated in a high-frequency range, they are subject to interference from the outside because their electromagnetic shields become weak.
DISCLOSURE OF THE INVENTION
According to one aspect of the invention, a base substrate for mounting a plurality of bare semiconductor chips (also described throughout the present specification as “chip devices”) thereon has first and second main surfaces. The first main surface has formed thereon at least one projection, and at least two recesses in which the bare semiconductor chip devices are to be mounted. The depth of the recesses are smaller than the length of the projection, and the recesses have a higher surface smoothness than the first main surface of the metal substrate.
According to another aspect of the invention, a base substrate made of metal or semiconductor has previously integrally formed on a main surface a plurality of recesses for mounting bare chip devices thereon, and a plurality of post-like projections as part of the base substrate. In addition, grooves are provided to surround the roots of some of the posts, and the bare chip devices including semiconductor elements or IC chips with conductive bumps provided on electrodes are mounted on the recesses. The bare chip devices are covered to bury with an insulating film. The insulating film and the bumps of the bare chip devices are flattened to have the same level. A wiring conductor pattern of a metal layer and an insulating film is formed thereon. The base substrate is etched or ground from the rear side to be thinned so that island-like conductors appear isolated by the insulating film, thus electrodes electrically isolated from a reference potential conductor being formed on the rear side of the base substrate.
In addition, the base substrate is previously worked on the rear main surface opposite to the main surface on which the bare chip devices are to be mounted, to form in that rear main surface a plurality of recesses which are deeper than the portion to be etched away or ground down when the base substrate is etched or ground from the rear main surface to be thinned, so that when the base substrate is cut into unit module sizes after the thinning process, the substrate of each unit module with the bare chip devices mounted on the first main surface can have recesses on its sides, and a metal cap of opposite recess is fitted in the recesses on the sides of the module to cover the unit module.
According to another aspect of the invention, a structure for mounting a plurality of bare semiconductor chip devices thereon can be produced by chemically partially etching a metal substrate having first and second main surfaces in order that at least one recess can be formed in the first main surface, and by mechanically working the first main surface of the metal substrate in order that at least two recesses for mounting the bare semiconductor chip devices thereon can be formed in an area with no projection provided, of the etched first main surface of the metal substrate. The recesses formed by the mechanical working step are smaller in depth than the length of the projection formed by the chemical etching step, and have a higher surface smoothness than the etched main surface of the metal substrate.
According to anot
Kagaya Osamu
Sekine Kenji
Yamada Hiroji
Yamasaki Matsuo
Yamashita Kiichi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Lee Eddie
Warren Matthew E.
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