Multi-chip module packaging system

Details Multi-chip module packaging system Multi-chip module packaging system

1993-11-30

1996-03-05

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

257686, 257693, 257696, 257777, 361730, 361732, 361735, 361746, H01L 2302

Patent

active

054970270

ABSTRACT:
A three dimensional logic cube comprises a base plate having two vertically mounted backplanes attached thereto. A plurality of horizontally stacked substrates are coupled by connectors to the backplanes, with enough clearance between adjacent substrates to ensure heat dissipating air or fluid flow between the substrates. Typically, the substrates are multi-chip modules having a plurality of logic and interconnect chips attached at die mounting locations. Preferably, the logic and interconnect chips are attached to the substrate using flip TAB frames. The substrate includes a pattern interconnect for connecting together all of the chips. The logic chip is based on a standard 10K-50K gate array design with 100 micron pad spacing. The interconnect chip uses an interconnect pattern to connect the logic chips. The interconnect chip uses a lead placement identical to the logic chip, so that a single TAB frame can be used for both chips.

REFERENCES:
patent: 4482938 (1984-11-01), Norden
patent: 4652974 (1987-03-01), Ryan
patent: 4688864 (1987-08-01), Sorel
patent: 4770640 (1988-09-01), Walter
patent: 5036473 (1991-07-01), Butts et al.
patent: 5095352 (1992-03-01), Noda et al.
patent: 5343075 (1994-08-01), Nishino
"Silicon Elevated Wireless Module Method for Making Engineering Changes;" IBM Technical Disclosure Bulletin; vol. 31, No. 10; Mar. 1989; pp. 71-74.

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