Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor
Reexamination Certificate
2000-08-31
2002-10-08
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
C257S623000
Reexamination Certificate
active
06462399
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the formation of a conductor trace-bearing carrier substrate from semiconductor material and the fabrication of a multi-chip module (“MCM”) from the substrate. More particularly, the present invention relates to forming the semiconductor carrier substrate as a segment of a micromachined silicon wafer and fabricating the MCM therefrom.
2. State of the Art
Chip On Board (“COB”) techniques are used to attach semiconductor dice to a printed circuit board, including flip chip attachment, wirebonding, and tape automated bonding (“TAB”). Flip chip attachment consists of attaching a “flip chip” to a printed circuit board or other substrate. A flip chip is a semiconductor chip that has a pattern or array of terminations spaced around an active surface of the flip chip for face-down mounting of the flip chip to a substrate. Generally, the flip chip active surface has one of the following electrical connectors: Ball Grid Array (“BGA”)—wherein an array of minute solder balls or other conductive material elements is disposed on the electrical connection locations on the active surface of a flip chip that attaches to the substrate, or Slightly Larger than Integrated Circuit Carrier (“SLICC”)—which is similar to a BGA, but having a smaller solder ball/conductive material element pitch (spacing) and diameter than a BGA.
Flip chip attachment requires (in the case of solder ball connections) the formation of solder-joinable contact sites or terminals on the metal conductors of a carrier substrate such as a printed circuit board (“PCB”), which sites are a mirror-image of the solder ball arrangement on the flip chip. The terminals on the substrate are usually surrounded by non-wettable barriers so that when the solder balls of the bond pads are placed in contact with the chip contact sites to melt and merge (“reflow”), surface tension holds the semiconductor chip by solder columns, suspending it above the substrate. After cooling, the chip is essentially brazed face-down to the carrier substrate by these very small, closely-spaced solder column interconnections. An insulative underfill encapsulant, such as an epoxy, is then generally disposed between the semiconductor die and the substrate for environmental protection and to enhance the attachment of the die to the substrate.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. To meet these challenges, attention has been directed to wafer level packaging. U.S. Pat. No. 4,670,770 issued Jun. 2, 1987 to Tai (“the '770 patent”) illustrates wafer level integrated circuits formed by placing “flipped” semiconductor chips on a wafer substrate. The wafer substrate carries solder metal contacts for attaching to metallic contacts on the semiconductor chips. However, the '770 patent requires specialized metallic contacts on the semiconductor chips to make contact with the solder metal contacts on the wafer substrate. These specialized contacts increase the cost of manufacturing the assembly because of the additional fabrication steps required.
Silicon wafers have also been used as carrier substrates for temporary electrical connection with an unpackaged semiconductor die for testing, such as disclosed in commonly-owned U.S. Pat. Nos. 5,326,428, 5,478,779, 5,483,741, 5,559,444, and U.S. patent application Ser. No. 08/387,687, each hereby incorporated herein by reference. The patents and application generally disclose raised contact members with sloped walls formed on a silicon wafer by an anisotropic etch process. The raised contact members have one or more projections at their outer ends adapted to penetrate contact locations (bond pads) on the semiconductor die under test and to pierce any residual oxide or other insulating material on the surface of the semiconductor die bond pads to establish an ohmic connection therewith. However, as these projections penetrate the surface of the die bond pads, on the semiconductor die under test to ensure good electrical connection, such penetration may, in some instances, degrade the physical integrity of the bond pad, or might pierce right through the bond pads making physical contact to the devices underneath, damaging and destroying them.
None of the prior art uses of wafers in wafer level semiconductor die packaging and testing as described above teach a cost efficient method of forming a wafer level carrier substrate which can be used for packaging or testing of semiconductor dice, and that does not require any specialized processing steps or which will not damage the bond pads of the semiconductor chip. Furthermore, these prior art techniques address only temporary connection between the bond pads and the substrate. Therefore, it would be advantageous to develop a technique for forming a carrier substrate from a silicon wafer which would achieve these goals while utilizing known semiconductor device fabrication techniques.
SUMMARY OF THE INVENTION
The present invention enables semiconductor packaging at a wafer level by forming an MCM from a micromachined carrier substrate, preferably of silicon. The formation of the micromachined substrate begins with providing a substrate of semiconductor material such as monocrystalline silicon (traditional wafer), silicon-on-glass, or silicon-on-sapphire, germanium, or ceramic, which is coated on one surface with a masking material, such as a layer of silicon nitride (Si
3
N
4
). The mask material is selectively etched to form strips across the surface of the substrate. The substrate is then etched except under the protective mask strips to form elongated mesas having sidewalls extending to a lower substrate surface. It is, of course, understood that groups of the strips may be placed in mutually transverse orientation to form “box canyons” of mesas adapted to receive a semiconductor chip with bond pads arrayed about the periphery of its active surface.
After mesa formation, the remaining mask material is removed, preferably using a wet etch. An insulating or dielectric layer is then formed on the substrate, including the elongated mesas and sidewalls. The insulating layer is preferably formed by oxidizing the substrate and may be accomplished by exposing the substrate to an oxidizing atmosphere in a reaction chamber. Other insulating techniques include deposition of silicon dioxide or silicon nitride by chemical vapor deposition (CVD), and injecting TEOS (tetraethyl-orthosilane) into the reaction chamber to grow silicon dioxide (SiO
2
) at a temperature of about 400° C. Silicon dioxide is preferred due to its low dielectric constant, which results in reduced capacitance and increased signal speed on the substrate traces. Other dielectrics such as silicon nitride can also be employed.
A conductive material layer is then formed on the insulating layer. The conductive material layer can be any known low-resistivity material such as a metal, preferably copper. The conductive material layer is then patterned and etched to form or define conductive traces on the dielectric-covered substrate surface. The conductive traces can be patterned to route signals between semiconductor dice carried on the substrate and/or to circuitry external to the substrate. A stack of conductive materials such as copper-coated palladium can also be used.
It is understood that the conductive traces can be formed by a number of alternate conventional techniques other than patterning and etching a metal layer discussed above, such as: depositing a conductive paste on the substrate by silk screening the conductive traces directly thereon; directly extruding a conductive paste to form the conductive traces; or applying a second insulating layer on the first insulating layer, etching a trough in the second insulating layer, filling the trough with a conductive material, and removing the excess conductive material. The conductive traces are preferably formed in the vicinity of chip-mounting sites
Cao Phat X.
Traskbritt
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