Multi-chip module and method for forming and method for...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices

Reexamination Certificate

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C257S758000, C257S532000, C257S528000

Reexamination Certificate

active

06882045

ABSTRACT:
A method for deplating defective capacitors comprising forming a plurality of capacitors on a semiconductor substrate, forming a plurality of metal contacts on the plurality of capacitors, and depositing a layer of photoresist on the semiconductor substrate. The photoresist layer is patterned so that the plurality of metal contacts are exposed, which are then contacted with an electrically conductive solution. The metal contacts, which are disposed over defective capacitors, are subsequently deplated. A method for forming a multi-chip module comprising forming a thin-film polymeric interconnect structure having a pair of sides, one of which is disposed on a silicon substrate having active or passive devices and the other of which has a computer chip mounted thereon. A multi-chip module formed by the method.

REFERENCES:
patent: 3655540 (1972-04-01), Irvin
patent: 3791858 (1974-02-01), McPherson et al.
patent: 3867272 (1975-02-01), Rust et al.
patent: 3976524 (1976-08-01), Feng
patent: 4045312 (1977-08-01), Satoshi
patent: 4181755 (1980-01-01), Liu et al.
patent: 4248683 (1981-02-01), Shaw
patent: 4614021 (1986-09-01), Hulseweh
patent: 4729970 (1988-03-01), Nath et al.
patent: 4749454 (1988-06-01), Arya et al.
patent: 4782028 (1988-11-01), Farrier et al.
patent: 4908940 (1990-03-01), Amano et al.
patent: 4915983 (1990-04-01), Lake et al.
patent: 4921777 (1990-05-01), Fraenkel et al.
patent: 4980034 (1990-12-01), Volfson et al.
patent: 4984358 (1991-01-01), Nelson
patent: 5063175 (1991-11-01), Broadbent
patent: 5071518 (1991-12-01), Pan
patent: 5091289 (1992-02-01), Cronin et al.
patent: 5097393 (1992-03-01), Nelson et al.
patent: 5106461 (1992-04-01), Volfson et al.
patent: 5118385 (1992-06-01), Kumar et al.
patent: 5137597 (1992-08-01), Curry, II et al.
patent: 5162260 (1992-11-01), Leibovitz
patent: 5202018 (1993-04-01), Horányl et al.
patent: 5283081 (1994-02-01), Kata et al.
patent: 5287619 (1994-02-01), Smith et al.
patent: 5316974 (1994-05-01), Crank
patent: 5337466 (1994-08-01), Ishida
patent: 5464653 (1995-11-01), Chantraine et al.
patent: 5512514 (1996-04-01), Lee
patent: 5543585 (1996-08-01), Booth et al.
patent: 5591678 (1997-01-01), Bendik et al.
patent: 5640049 (1997-06-01), Rostoker et al.
patent: 5654237 (1997-08-01), Suguro et al.
patent: 5656548 (1997-08-01), Zavracky et al.
patent: 5656552 (1997-08-01), Hudak et al.
patent: 5699613 (1997-12-01), Chong et al.
patent: 5716881 (1998-02-01), Liang et al.
patent: 5734555 (1998-03-01), McMahon
patent: 5770487 (1998-06-01), Maas et al.
patent: 5784261 (1998-07-01), Pedder
patent: 5784782 (1998-07-01), Boyko et al.
patent: 5807783 (1998-09-01), Gaul et al.
patent: 5811879 (1998-09-01), Akram
patent: 5830533 (1998-11-01), Lin et al.
patent: 5834845 (1998-11-01), Stolmeijer
patent: 5838545 (1998-11-01), Clocher et al.
patent: 5843806 (1998-12-01), Tsai
patent: 5843839 (1998-12-01), Ng
patent: 5851845 (1998-12-01), Wood et al.
patent: 5856937 (1999-01-01), Chu et al.
patent: 5859397 (1999-01-01), Ichinose et al.
patent: 5863412 (1999-01-01), Ichinose et al.
patent: 5863829 (1999-01-01), Nakayoshi et al.
patent: 5866441 (1999-02-01), Pace
patent: 5872025 (1999-02-01), Cronin et al.
patent: 5872700 (1999-02-01), Collander
patent: 5877034 (1999-03-01), Ramm et al.
patent: 5891606 (1999-04-01), Brown
patent: 5891799 (1999-04-01), Tsui
patent: 5916453 (1999-06-01), Beilin et al.
patent: 6013417 (2000-01-01), Sebesta et al.
patent: 6316838 (2001-11-01), Ozawa et al.
patent: 6608371 (2003-08-01), Kurashima et al.
patent: 56-116697 (1981-09-01), None
patent: 63-244796 (1988-10-01), None
Pan et al., “A Planar Approach to High Density Copper-Polymide Interconnect Fabrication,” pp. 174-189, Proceeding of the Technical Conference—8thInt'l Electronics Packaging Conference (1988).
Iwasaki et al., “A Pillar-Shaped Via Structure in a Cu-Polymide Multilayer Substrate,” pp. 127-131, Proceedings of the 1989 Japan International Electronic Manufacturing Technology Symposium.

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