Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-01-30
2002-05-14
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S723000, C257S777000
Reexamination Certificate
active
06388313
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention:
This invention relates to integrated circuit packaging technology, and more particularly, to a multi-chip module used to pack two or more semiconductor chips in a stacked manner and method of fabricating the same.
2. Description of Related Art:
Multi-chip packaging technology is used to pack two or more semiconductor chips over substrate or leadframe in one single package module, so that one single package module is capable of offering a manifold level of functionality or data storage capacity. Conventionally, there are two schemes to mount two or more chips on a single substrate. One scheme is to mount these chips in a side-by-side manner over the substrate. This scheme allows the resulted multi-chip module to be low in height, but one drawback is that it would require a substrate of a large surface area to implement. During SMT (Surface Mount Technology) process, a larger substrate would be more easily subjected to warpage, resulting in undesired delamination or peeling of the chips from the substrate. The finished product of the multi-chip module would therefore have reliability concern. Another scheme is to mount the chips in a stacked manner. Although this scheme would make the resulted multi-chip module greater in height, it can help to prevent the above-mentioned problem of delamination or peeling due to the use of a large substrate.
FIG. 6
is a schematic diagram showing a conventional stacked type of multi-chip module. As shown, this multi-chip module
1
a
includes a first chip
10
a
and a second chip
12
a
, wherein the first chip
10
a
is adhered to a substrate
11
a
and the second chip
12
a
is mounted over the first chip
10
a
in a stacked manner. The first chip
10
a
is electrically connected to the substrate
11
a
by means of a first set of gold wires
13
a
, and the second chip
12
a
is electrically connected to the same by means of a second set of gold wires
14
a
. One drawback to this multi-chip module, however, is that the second chip
12
a
should be smaller in size than the first chip
10
a
due to the reason that part of the surface of the first chip
10
a
is occupied by the first set of gold wires
13
a
. This restriction limits the use of this multi-chip module to pack chips of the same size or variably-selected sizes.
One solution to the foregoing problem is disclosed in U.S. Pat. No. 5,793,108, which is illustrated in FIG.
7
. This patented multi-chip module
1
b
is characterized by that it includes two chips
10
b
,
12
b
which are mounted in a stacked back-to-back manner over a die pad
110
b
, wherein the first chip
10
b
has its active surface adhered to the die pad
110
b
and electrically connected to the leads
111
b
by means of a first set of gold wires
13
b
, and the second chip
12
b
has its non-active surface adhered to the non-active surface of the first chip
10
b
and electrically connected to the leads
111
b
by means of a second set of gold wires
14
b
. This stacked back-to-back structure allows two chips of the same size to be packed in the same module. One drawback to this multi-chip module, however, is that it would be unsuitable for use to pack two chips of the same functionality due to the reason that it would be difficult to arrange the I/O pads on the two chips for external connections.
Another solution that can pack two or more chips of the same size or variably-selected sizes in the same module is disclosed in U.S. Pat. No. 5,323,060, which is illustrated in FIG.
8
. As shown, this patented multi-chip module
1
c
can be used to pack a plurality of chips, for example four chips
10
c
,
11
c
,
12
c
,
13
c
, of the same size. These chips
10
c
,
11
c
,
12
c
,
13
c
are mounted in a stacked manner and adhered to each other by means of adhesive layers
14
c
. The first chip
10
c
is electrically connected to the leads
157
c
by means of a first set of gold wires
16
c
; the second chip
11
c
is electrically connected to the same by means of a second set of gold wires
17
c
; the third chip
12
c
is electrically connected to the leads
157
c
by means of a third set of gold wires
18
c
; and the fourth chip
13
c
is electrically connected to the leads
157
c
by means of a fourth set of gold wires
19
c
. One drawback to this patented multi-chip module, however, is that the adhesive layers
14
c
should be greater in height than those parts of the gold wires that are positioned above the chips
10
c
,
11
c
,
12
c
,
13
c
, and smaller in horizontal extent than the chips
10
c
,
11
c
,
12
c
,
13
c
so that they would not touch the gold wires
16
c
,
17
c
,
18
c
,
19
c
. This structure allows the chips
10
c
,
11
c
,
12
c
,
13
c
to be variably sized according to actual needs. This patented multi-chip module, however, has the following drawbacks. First, only the bond pads on the bottommost chip
10
c
are under-supported, while the bond pads on the overlaid chips
11
c
,
12
c
,
13
c
are suspended without undersupport. Therefore, during wire-bonding process, it would easily cause these overlaid chips
11
c
,
12
c
,
13
c
to be cracked. Second, in the event that the adhesive layers
14
c
are inadequately dimensioned to the required thickness, it would make the wire-bonding process for the bonding wires
16
c
,
17
c
,
18
c
,
19
c
to be difficult to carry out. Third, it would make the resulted multi-chip module exceedingly great in height and therefore would not meet compactness requirement. Fourth, due to the existence of the adhesive layers
14
c
between the chips
10
c
,
11
c
,
12
c
,
13
c
, there would exist voids between the chips
10
c
,
11
c
,
12
c
,
13
c
after the multi-chip module is encapsulated through molding process, which would adversely degrade the quality of the resulted multi-chip module.
Still another solution that can pack two or more chips of the same size or variably-selected sizes in the same module is disclosed in U.S. Pat. No. 5,721,452, which is illustrated in FIG.
9
. As shown, this patented multi-chip module
1
d
includes a first chip
10
d
and a second chip
12
d
. The first chip
10
d
has two rows of edge-located bond pads
100
d
, and the second chip
12
d
also has two rows of edge-located bond pads
120
d
. This patented multi-chip module is characterized by that the first chip
10
d
is stacked in a crossed manner over the second chip
12
d
, so that the bond pads
100
d
on the first chip
10
d
can be separately positioned from the bond pads
120
d
on the second chip
12
d
, allowing a first set of gold wires
13
d
to be connected to the bond pads
100
d
on the first chip
10
d
and a second set of gold wires
14
d
to be connected to the bond pads
120
d
on the second chip
12
d
without difficulty. One drawback to this patented multi-chip module, however, is that the bond pads
120
d
on the overlaid second chip
12
d
are suspended without undersupport, which would easily cause the second chip
12
d
to be cracked during the wire-bonding process for the second chip
12
d
. One solution to this problem is to dispose a pillar (not shown) beneath the bond pads
120
d
to undersupport the bond pads
120
d
. One drawback to this solution, however, is that it would make the overall fabrication process more complex and costly to implement. Moreover, by this patented technology, the bond pads
100
d
on the first chip
10
d
can only be edge-located but cannot be peripherally-located; and the bond pads
120
d
on the second chip
12
d
can only be edge-located but cannot be peripherally- located; otherwise, it would make the wire-bonding process difficult to carry out.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a multi-chip module and method of fabricating the same, which can be used to pack two or more chips of variably-selected sizes in the same module.
It is another objective of this invention to provide a multi-chip module and method of fabricating the same, which can prevent the chips from being cracked during wire-bonding process.
It is st
Chen Chin-Te
Lee Ming-Hsun
Corless Peter F.
Edwards & Angell, LLP.
Jensen Steven M.
Potter Roy
Siliconware Precision Industries Co. Ltd.
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