Multi-chip integrated circuit module and method for fabrication

Details Multi-chip integrated circuit module and method for fabrication Multi-chip integrated circuit module and method for fabrication

1993-02-09

1994-04-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437211, 437214, 437217, 437220, H01L 2160

Patent

active

053066707

ABSTRACT:
A multi-chip integrated circuit module includes a supporting layer of laminate material over which a high-density interconnect structure is formed. The laminate layer includes a first upper laminate layer (10) having a hole (14) disposed therein for receiving an integrated circuit chip die (56). A lower core laminate layer (16) having a conductive layer (18) and conductive layer (20) disposed on opposite sides thereof is laminated to the lower surface of the layer (10). Plated-through holes (36), (38) and (40) are formed through the two layers (10) and (16) to connect the conductive layer (20) with a conductive layer (12) on the upper surface of the layer (10). A high-density interconnect layer includes two laminate layers (126) and (138), each having vias formed therethrough and via interconnect structures disposed on the surfaces thereof. The via interconnect structures in the layer (126) allow for connections from the die (56) to the conductive layer (12). The via interconnect structures formed in the layer (138) allow interconnection from the upper surface of layer (138) to via interconnects formed in the layer (126). An I/O connector is interfaced with select ones of the plated-through holes with pins (162) and (164). This allows an interface from the module to an operating system through pins (166).

REFERENCES:
patent: 4633573 (1987-01-01), Scherer
patent: 4874721 (1989-10-01), Kimura et al.
patent: 5098864 (1992-03-01), Mahulikar
patent: 5102829 (1992-04-01), Cohn
patent: 5188984 (1993-02-01), Nishiguchi
patent: 5206188 (1993-04-01), Hiroi et al.

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