Multi-chip device partitioning process

Details Multi-chip device partitioning process Multi-chip device partitioning process

1997-06-24

1998-07-21

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, 364491, 364578, G06F 1750

Patent

active

057842906

ABSTRACT:
An efficient method for partitioning, for example, FPGA devices is described which optimizes the number of devices required to implement a design. The method involves generating a hierarchical graph of a feasible bipartition of the cells of the design. Feasible pairs are merged, followed by flattening of the hierarchical graph. The number of I/O pins of the new partition is then reduced, upon which a hierarchical graph is derived. A perturbed partition is then generated, followed by restoration of feasibility.

REFERENCES:
Kunzar et al. "Cost Minimization of Partitions into Multiple Devices" 30th ACM/IEEE Design Aut. Conf., pp. 315-320, 1993.
Deng "An Investigation on Parasitic Couplings and Feedback Loops in the CMOS Circuits," IEEE, pp. 864-867.

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