Multi-chip chip scale package

Details Multi-chip chip scale package Multi-chip chip scale package

1999-02-01

2001-05-22

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With large area flexible electrodes in press contact with...

C257S623000, C257S701000, C257S706000, C257S707000, C257S777000, C257S778000, C257S668000, C257S677000, C257S690000, C257S713000

Reexamination Certificate

active

06236109

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor packaging structure, and more particularly, to a multi-chip chip scale package (CSP).
2. Description of the Related Art
As the technology of semiconductor fabrication grows more and more advanced, the relevant techniques have to be further developed to coordinate the requirements of the semiconductor devices. The fabrication process of a semiconductor device typically includes three stages. In the first stage, an epitaxy technique is used for the formation of a semiconductor substrate. Semiconductor devices such as metal-oxide semiconductor (MOS) and multilevel interconnection are fabricated on the substrate in the second stage. The third stage is the packaging process. It is now a leading trend for fabricating a device or an electronic product with a thin, light, and small dimension, that is, with a higher integration for semiconductor devices. In terms of packages, many techniques such as chip scale package, multi-chip module (MCM) have been developed to obtain a high integration. The development of the fabrication technique with a line width of 0.18 &mgr;m has evoked a great interest and intensive research to further decrease the package volume. It is thus one of the very important package techniques to arrange more than one chips into a single package. In a multi-chip package, chips of processor, memory, including dynamic random access memory (DRAM) and flash memory, and logic circuit can be packed together in a single package to reduce the fabrication cost and the packaging volume. Furthermore, the signal transmission path is shortened to enhance the efficiency. The multi-chip IC packaging technology may also be applied to a multi-chip system with variable functions and operation frequencies, for example,
1. A system comprises memory chips, microprocessors, resistors, capacitors, and inductors.
2. A system comprises memory chips (DRAM), logic circuit chips, and memory chips (Flash memory),
3. A system comprises analog chips, logic circuit chips, memory chips (including DRAM, SRAM, Flash memory), resistor, capacitor, and inductor.
In
FIG. 1
, a conventional multi-chip module is shown. A multi-level printed circuit board (PCB) is typically applied as a substrate of the to the carrier of a multi-chip module. More than one chips
12
are adhered on the substrate
10
by insulation glue
14
. The bonding pads on the chip
12
are electrically connected with the terminals on the substrate
10
by conductive wires
16
. In addition to wire bonding, the connection between the chip
12
and the substrate
10
can also be established by flip chip or controlled collapse chip connection (C4) with the formation of a bump. A resin
18
is used to seal the chip
12
, and the electrical connection between the whole package and a printed circuit board can be achieved by ball grid array (BGA) which use solder balls
20
to connect the terminals on the printed circuit board. The drawback of this conventional multi-chip module includes a large surface is occupied since chips are packaged on a same side of surface. Therefore, the volume of the package is large, and the signal path between chips is long. In addition, though the volume of the package can be reduced by using flip chip technique to achieve the connection between the chip and the carrier, a known good die (KGD) method has to be used for testing. A low yield and a high cost are thus resulted.
To further shrink the volume of package, a face to face multi-chip package is disclosed in U.S. Pat. No. 5,331,235. In
FIG. 2
, this multi-chip package comprises two chips
30
and
32
disposed face to face by way of tape automatic bonding (TAB). For the part of inner lead bonding (ILB), two chips
30
,
32
having bumps
34
,
36
to electrically connect the film carrier
38
. In the part of outer lead bonding (OLB), the chips
30
,
32
connect to a lead frame
40
. A solder ball
42
is formed between the chips
30
,
32
. The chips
30
,
32
, the film carrier
38
and the lead frame
40
are then molded resin
44
. This multi-chip package uses tape automatic bonding technique. The electrical connection between chips and printed circuit board is achieved by the installation of a lead frame or other carriers. The signal transmission path is lengthened. In addition, a large thickness and surface area are resulted by using the molding material (resin) of package. The applicability is reduced, and the heat dissipation is not effective. Moreover, this kind of package can not be applied to high frequency products.
SUMMARY OF THE INVENTION
The invention provides a multi-chip chip scale package with a reduced thickness and surface area. The surface area is substantially the same or slightly bigger than the largest chip being packaged therein.
The multi-chip chip scale package has a shortened signal transmission path to enhance the performance of the chips.
The multi-chip chip scale package mentioned above has an enhanced performance of heat dissipation. The heat dissipation can be performed by ways of metal plate or printed circuit on a printed circuit board, or alternatively, by an additional heat dissipation apparatus.
In addition, the test of chip package can be performed during package process without using known-good die method.
To achieve the above-mentioned objects and advantages, a multi-chip chip scale package is provided. A film carrier is used to carry two chips in different sizes. Using flip chip technique, these two chips are disposed face-to-face on two sides of the film carrier. The chips each has a bump connecting to the film carrier. An insulation material is infilled between the chips, while the other side of each of the chips is bared. Accordingly, the thickness of the package is reduced, and the performance of heat dissipation is enhanced. Moreover, conductive wires are formed on the film carrier to directly connect an external signal. The signal transmission path is shortened with going through an additional carrier.
While arranging the multi-chip chip scale package on a printed circuit board, the chip may has a side directly connected to a printed circuit or metal plate on the printed circuit board to provide an advantageous the heat dissipation. An additional heat dissipation apparatus may also installed on a surface of the other chip in the far end of the printed circuit board. The heat dissipation effect is thus further enhanced. In addition, at least one locating hole is formed on the insulation film and filled by the insulation material, so that the chip can be connected to the film carrier more stably. Thus, an improved packaging quality and an enhanced reliability are obtained.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5182631 (1993-01-01), Tomimuro et al.
patent: 5477082 (1995-12-01), Buckley et al.
patent: 5757080 (1998-05-01), Sota
patent: 5790384 (1998-08-01), Ahmad et al.
patent: 5814882 (1998-09-01), Shimada et al.
patent: 5901041 (1999-05-01), Davies et al.
patent: 5936305 (1999-08-01), Akram
patent: 6054337 (2000-04-01), Solberg
patent: 402122533 (1990-05-01), None

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