Multi-channel serdes receiver for chip-to-chip and backplane...

Pulse or digital communications – Receivers – Angle modulation

Reexamination Certificate

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Reexamination Certificate

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07426247

ABSTRACT:
A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes:(1) a central frequency synthesizer configured to provide both in-phase and quadrature-phase clock signals and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer. Each of the plurality of channel-specific receivers is configured to receive and deserialize a data signal and include a clock recovery circuit having a phase detector and a phase interpolator. The interpolator is configured to receive the clock signals from the central frequency synthesizer and couple the phase detector and the central frequency synthesizer.

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Younis et al. “A Low Jitter, Low Power, CMOS 1.25-3.125Gbps Transceiver”, IEEE, Sep. 2001, p. 1-4.

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