Coded data generation or conversion – Analog to or from digital conversion – Multiplex
Utility Patent
1999-02-12
2001-01-02
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Multiplex
Utility Patent
active
06169505
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to digital-to-analog conversion and, in particular, to digital-to-analog conversion using multi-channel, parallel digital-to-analog converters that have from a few to many thousands of channels all having accurately-matched conversion characteristics.
BACKGROUND OF THE INVENTION
The growing power of digital signal processors (DSPs) has increased the need for analog-to-digital converters to convert analog signals originating in the physical world to digital signals, and digital-to-analog converters to restore digital signals to the analog signals required in the physical world. At the same time, the increased processing power of DSPs has created the need to increase the throughput of analog-to-digital converters and digital-to-analog converters. One approach to increasing the speed of a digital-to-analog converter is to increase the speed of the converter itself; another is to perform the conversion using parallel signal paths. While not all applications lend themselves to conversion using parallel signal paths, for those that do, conversion using parallel signal paths offers advantages in power, performance or both. Moreover, conversion using parallel signal paths can provide a faster conversion rate than the fastest conversion rate of a single converter.
A specific example of an application in which conversion using parallel signal paths works well is an array structure. An array structure typically has data paths that are independent in one or more dimensions. This structure allows N digital-to-analog converters working in parallel to generate N parallel analog signals to fill the array rather than using a single digital-to-analog converter to generate sequentially an analog signal for each element of the array.
One example of an array structure in which using parallel digital-to-analog converters offers advantages is the array of pixel circuits in a miniature video display based on a light valve that uses a ferroelectric liquid crystal material. Such a miniature video display can form part of a wearable eyeglass display that can be used to display computer graphics when connected to the video output of a computer, especially a laptop computer, and can be used to display video when connected to the video output of a TV receiver, a video cassette player or a DVD player, especially a portable DVD player. Such a miniature video display is described in U.S. patent applications Ser. Nos. 09/070,487 and 09/070,669, assigned to the assignee of this disclosure and incorporated herein by reference. One embodiment of the light valve of such a miniature video display includes an array of 1024×768 pixels, each including a reflective electrode driven by a respective pixel circuit. The pixel circuit converts an analog sample derived from an analog video signal into a two-state drive signal having a duty cycle that defines the apparent brightness of the pixel.
When the miniature video display just described is driven by a conventional analog video signal, analog samples are derived from each line of the analog video signal and are distributed via column busses to the pixel circuits in each row of the array. Recently, however, it has been proposed to use the video display just described as the viewfinder of a digital camera that generates a digital video signal. To drive the video display, the digital video signal generated by the camera must be converted to an analog signal by a digital-to-analog converter. Since the analog samples of each line of the video signal are distributed via the column buses, the required digital-to-analog conversion speed could be obtained by performing the conversion using 1024 parallel digital-to-analog converters, one for each column.
However, the inherent mismatch problems of analog circuitry is a major drawback in using independent, parallel digital-to-analog converters as just described. Although great care can be taken to minimize the effects of non-ideal circuit characteristics and physical device mismatching, it is not usually possible to avoid completely the artifacts produced by these factors. In the example just described, mismatches between the digital-to-analog converters cause vertical banding in the picture generated by the miniature video display. Such vertical banding is easily noticeable in pictures lacking fine detail.
Techniques that mitigate the effects of analog circuit mismatching exist and are often applied to simple analog circuits such as amplifiers. However, applying such mitigation techniques to complex analog circuits such as digital-to-analog converters is less straightforward and usually involves significant additional circuitry. Such additional circuitry increases power consumption and cost. When an application, such as that described above, calls for massively-parallel digital-to-analog conversion, the correction techniques required to mitigate physical device mismatching and non-ideal circuit characteristics become cumbersome and unwieldy.
One conventional way of performing multiple parallel digital-to-analog conversions that avoids the mismatch issues described above is to use a single digital-to-analog converter preceded by a digital multiplexer and followed by an analog demultiplixer, as shown in FIG.
1
. In this, the multi-channel digital-to-analog converter
10
is composed of the single high-speed digital-to-analog converter
12
preceded by the digital multiplexer
14
and followed by the analog demultiplexer
16
. The N inputs of the multiplexer are connected to the N parallel digital input lines
18
. The output of the multiplexer is connected to the input of the digital-to-analog converter. The analog output of the digital-to-analog converter is connected to the input of the demultiplexer. The N outputs of the demultiplexer are connected to the N parallel analog output lines
20
.
The multiplexer
14
multiplexes the N channels (N=4 in the highly-simplified example shown) of digital input data received on the parallel input lines
18
to generate a single serial digital input. The serial digital input is fed to the digital-to-analog converter
12
. The demultiplexer
16
demultiplexes the analog output from the digital-to-analog converter into the N parallel analog output lines
20
.
The multi-channel digital-to-analog converter shown in
FIG. 1
avoids the drawbacks of multiple, parallel, independent digital-to-analog converters, but has three significant drawbacks of its own. First, the demultiplexer
16
can introduce errors between its input and its outputs that can be different for each output. Thus, this approach does not offer a complete solution to the mismatch problem described above.
Second, the operational speed requirements of the digital-to-analog converter
12
rapidly become unattainable as the number of parallel channels increases. For example, a sequential-color video display having a VGA resolution in which N=640, and a frame rate of 225 Hz (75 Hz×3 primary colors) would typically have a line rate of 108 kHz. Accounting for switching overhead, a line rate as high as 200 kHz is not unreasonable. To provide 640 analog samples per line, the digital-to-analog converter
12
would have to perform 128 million digital-to-analog conversions per second. In higher-resolution displays, N can approach 2,000 and the line rate can approach 1 MHz as refresh rates continue to increase. Such displays would require the digital-to-analog converter
12
to perform in excess of 1 billion (10
9
) digital-to-analog conversions per second. It is not practical to construct such converters using current mainstream CMOS technologies. Moreover, the power consumption of such high-speed converters makes them very unattractive for portable applications.
Third, due to the serial conversion processing performed by the digital-to-analog converter
12
, the individual parallel analog outputs are generated at different times and are transitory. To generate non-transitory analog outputs, each analog output would additionally include a track-and-hold circuit or a sam
Blalock Travis N.
Nishimura Ken A.
Agilent Technologie,s Inc.
Jean-Pierre Peguy
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