Multi-channel master/slave interprocessor protocol

Details Multi-channel master/slave interprocessor protocol Multi-channel master/slave interprocessor protocol

1999-07-21

2003-01-28

Etienne, Ario (Department: 2157)

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

Least weight routing

C709S238000, C709S245000

Reexamination Certificate

active

06513070

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to interprocessor communications. More specifically, the invention concerns interprocessor protocols providing reduced latency and complexity, as well as the ability to simultaneously transfer different types of data.
2. Background Art
Banks, credit unions and other financial institutions often image checks, deposit slips and other types of bank documents in order to process financial transactions efficiently. Document processing systems have therefore become quite prevalent in the industry. In the performance of these critical functions, document processing systems commonly contain multiple microprocessor elements that are responsible for different tasks within the machine. In addition to their individual processing responsibilities, these processor elements are required to communicate with each other. Latency occurs when a processor foregoes its own processing functions because it is waiting for a response from another processor. The lost time created by latency therefore significantly compromises the performance of multiple processor systems and has generally resulted in increased complexity in an effort to address the problem. It is therefore desirable to allow processors to maximize efficiency by performing internal processing whenever external communication is not absolutely necessary.
In addition to the concern for latency, modern systems also generally require processing elements to be able to transfer high-bandwidth compressed data such as images or diagnostic traces. The dual role for processors in multiple processor systems thus presents the necessity for high-throughput data transfer as well as efficient communication. Single-channel configurations fail to adequately address these concerns and significantly add to processing time.
Another shortcoming of current approaches is the inability to readily diagnose hardware and software errors. For example, diagnostic information must typically be accessed from the main communication channel, which creates additional processing and communication delays. It is further desirable to allow one of the processors to use DMA operations to perform other tasks while the data is being transferred. The ability of the DMA processor to get immediate notification once the transfer is complete would therefore provide increased efficiency.
SUMMARY OF THE INVENTION
In a first aspect of the invention a method for interprocessor communication comprises the steps of transferring low-latency information between a first processor and a second processor across a first channel, and transferring high-throughput information between a first processor and a second processor across a second channel. The method interrupts the first processor to transfer control information to the first processor. The control information controls transfer of information across the first channel and the second channel.
In a second aspect of the invention, an interprocessor configuration comprises a master processor having a DMA controller, a slave processor, and a multi-channel interface disposed between the slave processor and the master processor. The multi-channel interface has a first channel for transferring low-latency information and a second channel for transferring high-throughput information. This aspect of the invention also comprises a protocol flag interface disposed between the slave processor and the master processor wherein the protocol flag interface is operable to transfer first channel interrupts between the master processor and the slave processor.


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