Multi-channel junction gated field effect transistor and method

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357 20, 357 36, 357 55, H01L 2980

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039770176

ABSTRACT:
A multi-channel junction gated field effect transistor which gives good triode characteristics is formed on a substrate of semiconductor material of relatively low impurity concentration of a first conductivity type. A mosaic shape semiconductor gate region of the opposite conductivity type is formed in the substrate below one major surface thereof, the mosaic shape of the gate region forming a plurality of windows filled with portions of the substrate which thus provide channels leading to the main body of the substrate, the main body of the substrate providing the drain region for the transistor. A corresponding relatively thick mosaic shape insulating layer overlies the mosaic shape gate region has a plurality of windows, which windows are smaller than the windows of the gate region and of the same configuration, the windows of the insulating layer being aligned with the windows of the gate region. The source consists of two regions, one which is heavily doped with impurity of the first conductivity type and the second which has less doping than that of the first source region but of greater doping than the drain region and the channel regions. The first source region is completely within the windows of the insulating layer, while the second source region is partially within such windows and extends down as a tongue partially into the channel. Electrodes are provided for the source, gate and drain regions.
The substrate is preferably N-type silicon having a doping level of 10.sup.14 to 10.sup.15 atoms/cm.sup.3. The first source region preferably has a doping higher than 5 .times. 10.sup.19, while the second source region with its tongues has a doping level between 10.sup.16 and 10.sup.18 atoms/cm.sup.3. If the doping level of the second source region is 10.sup.18 atoms/cm.sup.3, it is possible to have the substrate doped to 10.sup.16 atoms/cm.sup.3.

REFERENCES:
patent: 3767982 (1973-10-01), Teszner et al.
patent: 3814995 (1974-06-01), Teszner
patent: 3841917 (1974-10-01), Shannon
patent: 3855608 (1974-12-01), George et al.
A. Morgan et al., "A Proposed Vertical Channel Variable Resistance Fet," Proc. IEEE, vol. 59, No. 5, May 1971, pp. 805-807.

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