Patent
1995-06-07
1996-11-12
Kim, Ken S.
39518319, 39518502, 39520008, 395866, 395309, G06F 15163
Patent
active
055749453
ABSTRACT:
A computer system with a coupling facility is provided with a plurality of processors and a plurality of intersystem channels coupled to the processors via a memory bus. The coupling facility includes a memory bus interface for the memory bus and a plurality of channels for coupling said channels to said processors. The memory bus interface includes an adapter with at least two hardware vectors provided for command detection, command isolation, and parallel testing of the error states of the intersystem channels, one which detects a command vector arrival, and a second which contains error state vector indicators. A LOCATE CHANNEL BUFFER (LCB) instruction is employed which performs a sense and reset operation on the command vector to identify and isolate a new command, and subsequently reads a vector of said error states vector indicator to determine the presence or absence of link errors.
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Elko David A.
Goldrian Gottfried A.
Goss Steven N.
Gregg Thomas A.
Helffrich Audrey A.
Augspurger Lynn L.
International Business Machines - Corporation
Kim Ken S.
Schiller Blanche E.
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