Multi-channel encoder/decoder

Details Multi-channel encoder/decoder Multi-channel encoder/decoder

1997-12-11

2001-02-13

Olms, Douglas W. (Department: 2732)

Multiplex communications

Channel assignment techniques

Details of circuit or interface for connecting user to the...

C370S400000, C370S419000, C370S439000, C370S458000

Reexamination Certificate

active

06188699

ABSTRACT:

FIELD
The present invention relates to a multi-channel encoder/decoder for encoding and decoding data communicated over multiple data links according to a data link control protocol such as High-Level Data Link Control (HDLC).
BACKGROUND
A number of devices have been developed which encode and decode data according to a data link control protocol such as HDLC. In providing service at the data link layer, previous devices typically encode or decode a single data stream. In modern digital communications systems, however, there is a need for higher density encoders and decoders capable of handling a variety of data streams. This need has grown as networks increasingly extend across a plurality of digital hierarchies. Often, legacy systems must be connected to emerging systems. Moreover, conventional carrier systems operate at a variety of interface rates, including 1.544 Mb/s, 2.048 Mb/s, 6.312 Mb/s, 8.488 Mb/s and 44.736 Mb/s. As is also well known, both the North American and the European standard for digital hierarchies define framing structures which support channelized communications. Each frame for a specified digital hierarchy consists of a cyclic set of consecutive time slots. For channelized connections in a selected digital hierarchy, a time slot occupying a specified position in the associated frame is allocated to a particular time-derived channel. The diversity of systems making up networks requires a new encoder and decoder capable of concurrently servicing a plurality of data links having different interface rates and having a multiplicity of possible channelized and unchannelized configurations.
Apart from the increasing need for a more robust encoder/decoder, prior art encoders and decoders generally provide simple interfaces to a control microprocessor, which requires the microprocessor to read and write all data to be transmitted and received to and from the encoder and decoder. Such devices are unsuitable for supporting a large number of data links operating at high speeds due to the unacceptably high burden of work placed on the microprocessor. In a high density device it is important that processor intervention is minimized in order to maintain quality of service over all channels and all links.
Accordingly, it is an object of the invention to provide a multi-channel encoder and decoder which fulfills the above needs in the art.
SUMMARY OF THE INVENTION
According to the invention there is provided a multi-channel network device for interfacing between a plurality of physical data links and a control processor, where each physical data link is characterized by a data stream of data packets communicated according to a data link control protocol. The multi-channel network device includes a plurality of receive-side line interfaces, with each receive-side line interface having at least one channel associated therewith. Each receive-side line interface is operative to receive incoming data packets from one of the physical data links such that each incoming data packet is received in at least one incoming data segment. Each receive-side line interface is also operative to determine a time-slot number for each incoming data segment arriving thereon.
The device includes a receive-side priority encoder circuit coupled to the receive-side line interfaces and operative to monitor the receive-side line interfaces and to process the incoming data segments arriving thereon according to a predetermined order of service. A receive-side channel assigner circuit coupled to the receive-side priority encoder circuit is operative to: (i) assign each incoming data segment processed by the receive-side priority encoder circuit to one of the channels; and (ii) pipeline the incoming data segments downstream. There is also provided a receive-side time-slice data processor coupled to the receive-side channel assigner circuit and operative to: (i) receive incoming data segments from the receive-side channel assigner circuit; and (ii) decode ones of the incoming data segments. A receive-side packet buffer processor is coupled to the receive-side time-slice data processor and includes a plurality of receive-side first-in first-out (FIFO) buffers. The receive-side packet buffer processor is operative to: (i) receive incoming data segments from the receive-side time-slice data processor; and (ii) buffer incoming data segments into the receive-side channel FIFO buffers according to the channel of each respective incoming data segment.
The multi-channel network device includes a control processor interface and a receive-side packet management circuit. The receive-side packet management circuit maintains a plurality of receive-side data packet descriptors, each receive-side data packet descriptor referencing a first memory block where one of the incoming data segments can be stored. The receive-side packet management circuit transfers incoming data segments stored in the receive-side channel FIFO buffers to the control processor via a control processor interface and manages the transfer with the receive-side data packet descriptors.
The receive-side priority encoder circuit can be operative to insert a null cycle periodically into the pipeline of incoming data segments so as to permit a microprocessor to access memory locations in a receive section of the device.
The receive-side channel assigner circuit may include a channel memory block and perform a channel lookup into the channel memory block for each incoming data segment by concatenating the link number of the respective receive-side line interface to the time-slot number of the respective incoming data segment.
In another embodiment, ones of the receive-side line interfaces may each include a clock gap detection circuit operative to determine time-slot alignment in channelized data packets. In one embodiment, each receive-side line interface includes a serial-to-parallel converter with a holding register to hold converted data, a time-slot counter coupled to the holding register and a clock activity monitor coupled to the time-slot counter. The time-slot counter is operative to increment each time the holding register is updated with data by the serial-to-parallel converter. The clock activity monitor includes a reference clock input line, a threshold register to store a predetermined value and a clock counter coupled to the reference clock input line and the threshold register and which increments at a reference clock rate.
In another embodiment, at least one of the receive-side line interfaces communicates with one of the physical data links at an interface rate different from the interface rates at which the other receive-side line interfaces communicate with their respective physical data links, such difference in interface rate exceeding a tolerance level encountered where a plurality of line interfaces operate at a single nominal data rate.
The receive-side time-slice data processor may include a plurality of state vectors, each state vector corresponding to one of the channels and having a plurality of data fields to identify a current state of processing data on the corresponding channel, wherein the receive-side time-slice data processor decodes ones of the incoming data segments according to information in the state vectors corresponding to the same channels as the ones of the incoming data segments. In another embodiment, the receive-side time-slice data processor is operative to offset the location of a first incoming data segment of an incoming data packet in the corresponding first memory location referenced by the respective receive-side data packet descriptor so as to permit header information to be pre-pended to the respective incoming data packet.
The receive-side packet buffer processor may include first, second and third receive buffer processors. The first receive buffer processor writes incoming data segments received from the receive-side time-slice data processor into the receive-side channel FIFO buffers. The second receive buffer processor transfers ones of the incoming data segments stored in the receive-sid

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