Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2006-06-20
2006-06-20
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S161000
Reexamination Certificate
active
07064700
ABSTRACT:
A pipelined analog to digital converter (“ADC”) as described herein is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase) using isolated input stages. The outputs of the input stages are concurrently sampled (every other clock phase) by a delay/holding and synchronization (“DHS”) stage. The DHS stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The DHS stage provides equal input loading for the input stages, which enhances the performance of the ADC.
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Braswell Brandt
Cassagnes Thierry
Cavanagh Christopher J.
Garrity Douglas A.
LoCascio David R.
Freescale Semiconductor Inc.
Ingrassia Fisher & Lorenz
Jean-Pierre Peguy
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