Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-08-22
2002-08-06
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
Reexamination Certificate
active
06429502
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to isolation techniques in semiconductor integrated circuits (ICs), and more particularly, to isolation techniques in silicon-on-insulator integrated circuits and isolation of radio frequency (RF) signals in silicon-on-insulator integrated circuits.
2. Description of Related Art
In semiconductor electronics, the general trend is to the production of integrated circuits having smaller and smaller form factors with improved performance and lower cost. In order to reduce form factors, more circuitry must be packed into less wafer real estate. As inter-device spacing shrinks, adjacent elements of the circuitry begin to interact with each other, reducing their performance. The basic measurement parameter that characterizes this effect is referred to as isolation. High isolation, and in particular, high RF isolation, implies that devices can be spaced closer together, and die size can be reduced. Minimum size in turn implies placement in smaller packaging and less space used on the application PCB Board. Also, because wafer processing costs are nearly independent of chip size, smaller circuits imply more die per wafer and thus a lower per die cost.
Isolation is parameter that is particularly important for analog integrated circuits (ICs). For example, isolation is important for ICs used in wireless communications applications. In general, wireless communications devices use high-frequency signals: 900 MHz to 1900 MHz for cellular phones and higher (up to 6 GHz) for other systems, such as wireless LANs. The well-known Bluetooth standard calls for operation in the unlicensed ISM band at 2.4 GHz. Signals at such frequencies, i.e., high radio frequencies (RF), are difficult to generate and control. They also have a tendency to interfere with each other, as they are easily coupled by parasitic properties present in all electronic components, including ICs. In ICs, many of the undesirable parasitic effects result from the conductive silicon substrate on which the circuits are fabricated. Poor isolation in a receiver, for example, can cause a portion of the local oscillator (LO) signal to appear at the output of the receiver and effectively be transmitted at the antenna. Wireless regulatory authorities limit the amount of spurious signal that can be radiated by the receiver, so limiting the amount of LO radiation is necessary to meet these specifications.
One type of semiconductor technology that is finding more use in bipolar applications is Silicon-On-Insulator (SOI) designs. With SOI, an insulating layer separates circuit devices from a solid silicon substrate. An example of one particular SOI technology is the bonded SOI BiCMOS process technology that is available from Hitachi Ltd. of Japan, and specifically, the Hitachi Ltd.
Device Development Center in Tokyo, Japan. This SOI BiCMOS process technology is also described in U.S. Pat. No. 5,661,329 entitled “Semiconductor Integrated Circuit Device Including An Improved Separating Groove Arrangement”, U.S. Pat. No. 5,773,340 entitled “Method of Manufacturing a BIMIS”, and U.S. Pat. No. 5,430,317 entitled “Semiconductor Device”, the complete disclosures of which are all hereby fully incorporated into the present application by reference for their teachings on SOI technologies.
Furthermore, this SOI BiCMOS process technology is also described in the paper entitled “A 0.35 um ECL-CMOS Process Technology on SOI for Ins Mega-bits SRAM's with 40 ps Gate Array” by T. Kikuchi, Y. Onishi, T. Hashimoto, E. Yoshida, H. Yamaguchi, S. Wada, N. Tamba, K. Watanabe, Y. Tamaki, and T. Ikeda of the Hitachi Ltd. Device Development Center, Tokyo, Japan, published in the IEDM Technical Digest, IEDM 95-923, in connection with the International Electron Devices Meeting, Dec. 10-13, 1995, 0-7803-2700-4, 1995 IEEE, the complete disclosure of which is hereby fully incorporated into the present application by reference. An SOI process technology is also described in the paper entitled “A 6 um2 bipolar transistor using 0.25-um process technology for high-speed applications” by T. Hashimoto, T. Kikuchi, K. Watanabe, S. Wada, Y. Tamaki, M. Kondo, N. Natsuaki, and N. Owada of the Hitachi Ltd. Device Development Center, Tokyo, Japan, published in IEEE BCTM 9.1, 0-7803-4497-9/98, 1998 IEEE, the complete disclosure of which is hereby fully incorporated into the present application by reference for its teachings on SOI technology.
Two types of substrate isolation techniques have heretofore been employed in SOI (such as the bonded SOI BiCMOS process technology available from Hitachi Ltd.). The first uses guard rings, and the second uses SiO
2
trench isolation. Guard rings are substrate contacts that enclose the area to be isolated. Dielectric trench isolation structures provide lateral barriers between circuit elements. These techniques isolate signals and minimize the undesired coupling that would otherwise limit performance for closely spaced adjacent circuit elements.
U.S. Pat. No. 5,661,329 (hereinafter '329) discloses an element separating groove arrangement formed to surround active regions to be formed with a semiconductor element. One disadvantage of this separating groove arrangement is that external RF power can still pass through the separating grooves to the active region. Specifically, the separating groove arrangement described in the '329 patent appears to be intended primarily for yield improvement and not for RF isolation. The '329 patent does not appear to address the problem of RF isolation and appears to show no intent to terminate electric fields created by RF power.
U.S. Pat. No. 5,644,157 (hereinafter '157) describes a polysilicon trench layered within a silicon oxide film formed to surround active regions to be formed with a semiconductor element. One disadvantage of utilizing a solid silicon oxide film is that external RF power or energy can avoid the polysilicon trench and pass through the solid silicon oxide film into the active regions. The '157 patent improves RF isolation on SOI technology, however, RF power can still penetrate into the active regions.
Thus, there is a need for an apparatus and method that provides improved RF isolation on SOI process technology.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor integrated circuit (IC) device that includes a substrate, an insulating layer formed on the substrate, and additional semiconductor layers formed on the insulating layer. A first isolation trench is formed in the additional semiconductor layers that extends to the insulating layer and that surrounds a first selected surface area of the additional semiconductor layers. A second isolation trench is formed in the additional semiconductor layers that extends to the insulating layer and that surrounds the first isolation trench and defines a guard ring region between itself and the first isolation trench. The first and second isolation trenches comprise isolation chambers that are smaller in size relative to the size of the isolation trenches. The isolation chambers are configured in several different manners. A ground conductor couples the guard ring region to a ground node.
The present invention also provides a semiconductor integrated circuit (IC) device that includes a substrate, an insulating layer formed on the substrate, a buried layer formed on the insulating layer, and an epitaxial layer of a first conductivity type formed on the buried layer. A first isolation trench comprising multiple isolation chambers is formed in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds a first selected surface area of the epitaxial layer. A second isolation trench comprising multiple isolation chambers is formed in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds the first isolation trench and defines a guard ring region between itself and the first isolation trench. A collector is implanted into the epitaxial layer in the guard
Hull Christopher D.
Librizzi Michael
Grebremaria Samuel A.
Jaquez & Associates
Jaquez, Esq. Martin J.
Lee, Esq. Allan Y.
Silicon Wave Inc.
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