Multi-board BGA package

Details Multi-board BGA package Multi-board BGA package

2001-07-05

2002-05-07

Tolin, Gerald (Department: 2835)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C174S050510, C257S738000, C257S787000, C361S705000, C361S784000

Reexamination Certificate

active

06385049

ABSTRACT:

FIELD OF THE INVENTION
The present invention is relating to an integrated circuit package, particularly to a BGA package having a plurality of circuit boards.
BACKGROUND OF THE INVENTION
An integrated circuit package with a window BGA packaging type (window Ball Grid Array package) is disclosed in U.S. Pat. No. 6,049,129 “chip size integrated circuit package”.
FIG. 8
is a cross-sectional view of the integrated circuit package
30
and
FIG. 9
is a top view of the integrated circuit package
30
. The integrated circuit package
30
comprises a silicon chip
50
having integrated circuit elements. The silicon chip
50
is attached onto a multi-layer printed circuit board
70
by an adhesive layer
60
. The multi-layer printed circuit board
70
has a plurality of routing strips
82
and corresponding conductive pads
10
, the pad
10
formed on the first surface
92
of printed circuit board
70
is bonded with solder ball
15
. An opening
86
is formed at the center area of the printed circuit board
70
for exposing the bonding pads
12
of silicon chip
50
to enable metal bonding wires
80
to pass through and electrically connect bonding pads
12
of chip
50
with routing strips
82
of printed circuit board
70
. The potting material
90
can be formed only by potting method because it is divided into two isolated portions around the perimeter of chip
50
and within the opening
86
(blocked by chip
50
), however a special mode with multi-injection is required in case of forming the potting material
90
by molding method. Besides, thermal stress of chip
50
and printed circuit board
70
caused by different coefficients of thermal expansion (CTE) results in the deformation of the integrated circuit package
30
.
SUMMARY
The main object of the present invention is to provide a multi-board BGA package that has a plurality of circuit boards formed on a same plane to hold at least a chip so as to reduce thermal stress caused by CTE mismatch.
The secondary object of the present invention is to provide a multi-board BGA package that comprises a plurality of circuit boards. A galley formed between adjacent circuit boards for passing through the metal bonding wires to connect chip with circuit boards, and also the package body is easy to be filled during molding process, besides a flexible space is provided for avoiding warping and having better elasticity.
The multi-board BGA package according to the present invention comprises:
a plurality of circuit boards, each circuit board having a first surface and a second surface, wherein the first surfaces of the plurality of circuit boards are formed on a same plane, and a galley is formed between adjacent circuit boards;
at least a chip adhered on the second surfaces of circuit boards, the chip having a plurality of bonding pads;
a plurality of metal bonding wires passing through the foregoing galley and connecting bonding pads of the chip and the circuit boards;
an encapsulant body formed in the galley and on the second surfaces of circuit boards; and
a plurality of solder balls bonds on the first surfaces of circuit boards.


REFERENCES:
patent: 3459998 (1969-08-01), Focarile
patent: 5359224 (1994-10-01), Heinen et al.
patent: 5717556 (1998-02-01), Yanagida
patent: 5739585 (1998-04-01), Akram et al.
patent: 6031730 (2000-02-01), Kroske
patent: 6049129 (2000-04-01), Yew et al.
patent: 6091140 (2000-07-01), Toh et al.
patent: 6177723 (2001-01-01), Eng et al.

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